Super-Junction Semiconductor Device Vertical Doping
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Solution Overview
Problem
As semiconductor devices shrink in size, they face challenges in maintaining high driving currents and low on-resistance while sustaining high breakdown voltages, due to reduced surface areas for doped regions which affect the performance of high-voltage MOSFETs in power semiconductor devices.
Innovation Solution
A semiconductor device with a super-junction structure is fabricated using a semiconductor-on-insulator substrate, with doped regions of opposite conductivity types formed through ion implantation and thermal diffusion, and a gate structure is created to cover these regions, increasing the cross-sectional area and improving current handling without increasing the surface area of the doped regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the device size is reduced, then the productivity and integration density are improved, but the driving current and on-resistance performance deteriorate due to reduced surface area of doped regions
Solution Approach 1:
The patent transitions from a planar surface structure to a three-dimensional vertical structure by forming doped regions that extend through multiple stacked semiconductor layers. This vertical extension in the depth dimension compensates for the reduced surface area, maintaining sufficient doped region volume for adequate driving current while achieving higher integration density through reduced footprint.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor layers are stacked vertically, with doped regions formed in each layer. The doped regions in different layers are positioned to overlap or align, creating a nested configuration that increases the effective cross-sectional area for current flow without increasing the device's surface footprint.
2Area of stationary object
If the device size is reduced, then the area occupied is decreased, but the on-resistance increases due to reduced cross-sectional area of doped regions
Solution Approach 1:
The patent addresses the on-resistance issue by extending doped regions vertically through multiple stacked semiconductor layers. This creates a larger effective cross-sectional area for current flow in the vertical dimension, compensating for the reduced horizontal footprint and thereby maintaining low on-resistance in the miniaturized device.
Solution Approach 2:
The patent uses composite doped region structures formed by stacking multiple semiconductor layers with alternating doping types. This composite structure optimizes the electrical properties by creating favorable doping profiles that reduce on-resistance while maintaining a compact device footprint.
3Reliability
If the surface area of doped regions is increased to improve driving current, then the device size must increase, but size reduction is required for modern semiconductor scaling
Solution Approach 1:
The patent resolves this contradiction by forming doped regions that extend vertically through multiple stacked semiconductor layers. This vertical extension increases the effective cross-sectional area for current flow without increasing the device's surface footprint, enabling adequate driving current in miniaturized devices.
Solution Approach 2:
The patent divides the doped region structure into multiple segments distributed across stacked semiconductor layers. Each layer contains doped regions that contribute to the overall current flow, and the segmented structure allows the total effective area to be distributed vertically rather than concentrated horizontally, achieving high driving current in a compact footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances driving currents and reduces on-resistance in high-voltage MOSFETs, enabling them to maintain performance as device size decreases, while maintaining high breakdown voltages and preventing latch-up effects through deep trench isolation.
Implementation Method 1
forming a first implanted region in a plurality of parallel and separated portions of the first semiconductor layer, wherein the first implanted region comprises a second conductivity type opposite to the first conductivity type
Implementation Method 2
performing a thermal diffusion process to diffuse the first implanted region in the first semiconductor layer and the implanted region in the second semiconductor layer into a first doped region and a second doped region, respectively
Data Source
AI summary
A semiconductor device includes: a plurality of stacked semiconductor layers; a plurality of composite doped regions separately and parallelly disposed in a portion of the semiconductor layers along a first direction; a gate structure disposed over a portion of the semiconductor layers along a second direction, wherein the gate structure covers a portion of the composite doped regions; a first doped region formed in the most top semiconductor layer along the second direction and being adjacent to a first side of the gate structure; and a second doped region formed in the most top semiconductor layer along the second direction and being adjacent to a second side of the gate structure opposite to the first side thereof.