Super Multiply Add Instruction Fusing Vector Operations
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Solution Overview
Problem
Current computing systems face inefficiencies in executing vector operations due to the need for separate multiplication and addition steps, which leads to cascading rounding errors and increased computational complexity.
Innovation Solution
The introduction of a 'super' multiply-add instruction (VSMADD) that fuses multiplication and addition operations, using a fused multiplier and Wallace tree circuitry to minimize rounding errors and reduce pipeline stages, allowing for simultaneous calculation of multiplication terms and subsequent addition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate multiplication and addition steps are used for vector operations, then computational accuracy is maintained through discrete operations, but computational efficiency deteriorates due to increased pipeline stages and cascading rounding errors
Solution Approach 1:
The patent merges multiplication and addition operations into a single fused multiply-add (FMADD) instruction that executes both operations simultaneously in one pipeline stage. This eliminates the sequential dependency between separate multiply and add operations, reducing the number of pipeline stages while maintaining computational accuracy through a single rounding operation instead of multiple sequential operations.
Solution Approach 2:
The fused multiply-add instruction maintains continuous computational flow by performing both multiplication and addition in a single uninterrupted operation. This eliminates the intermediate pause between separate operations and reduces the accumulation of rounding errors that would occur with discrete sequential steps, thereby improving both efficiency and accuracy.
2Device complexity
If multiple separate instructions are used for vector multiply and add operations, then operational flexibility is maintained, but device complexity increases due to additional pipeline stages and instructions
Solution Approach 1:
The fused multiply-add instruction serves multiple computational purposes within a single instruction format, supporting both scalar and vector operations, as well as different data types (single-precision and double-precision). This multi-functionality reduces the need for multiple separate instructions while maintaining operational flexibility across different computing scenarios.
Solution Approach 2:
The instruction set is segmented into different fused multiply-add variants (scalar FMADD, vector FMADD, single-precision, double-precision) that can be selected based on the specific computational requirements. This segmentation allows the system to maintain flexibility for different operations while using a unified instruction architecture that reduces overall device complexity.
Data Source
AI summary
A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address.