Super Neuron Processing Units for Spiking Neural Network Hardware
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Solution Overview
Problem
Existing artificial neural networks face inefficiencies in hardware implementation, particularly in spiking neural networks, due to cumbersome traditional computational techniques and the need for efficient handling of synaptic weights and plasticity parameters.
Innovation Solution
The method involves operating multiple super neuron processing units simultaneously, with each unit assigned a subset of artificial neurons, and interfacing these units with memory for contiguous access to synaptic weights and plasticity parameters, optimizing memory organization for efficient hardware implementation of spiking neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional computational techniques are used in spiking neural networks, then computational accuracy is maintained, but hardware efficiency and processing speed deteriorate
Solution Approach 1:
The patent segments the spiking neural network into multiple super neuron processing units, each handling subsets of neurons and their associated synapses. This segmentation enables parallel processing while maintaining the complexity of individual units at manageable levels, thus improving processing speed without overwhelming hardware resources.
Solution Approach 2:
The patent introduces a new dimension of organization by grouping synapses according to their post-synaptic neuron assignments rather than traditional pre-synaptic connections. This dimensional reorganization enables more efficient memory access patterns and contiguously accessible memory structures, improving hardware efficiency.
2Productivity
If memory is organized for traditional access patterns, then data structure simplicity is maintained, but memory access efficiency and throughput deteriorate
Solution Approach 1:
The patent reorganizes memory along a new dimension by grouping synapses according to their post-synaptic neuron assignments. This creates contiguously accessible memory structures where all synapses targeting a specific neuron are stored together, enabling efficient batch access and improving memory throughput without traditional access patterns.
Solution Approach 2:
The reorganized memory structure serves multiple functions simultaneously: it enables efficient access for spike propagation, supports contiguous memory access patterns, and facilitates parallel processing across multiple super neuron units. This multi-functionality improves throughput while managing complexity through unified memory organization.
3Productivity
If multiple processing units operate in parallel, then computational throughput is improved, but inter-unit communication overhead and synchronization complexity increase
Solution Approach 1:
The patent divides the neural network into multiple independent super neuron processing units that can operate in parallel. Each unit handles its assigned subset of neurons and synapses autonomously, reducing inter-unit communication overhead while maintaining high computational throughput through segmented parallel processing.
Solution Approach 2:
The patent performs preliminary organization of synapses by post-synaptic neuron assignment before parallel processing begins. This pre-organization enables each processing unit to independently access its required data without complex synchronization, reducing communication overhead while maintaining high throughput.
Data Source
AI summary
Certain aspects of the present disclosure support operating simultaneously multiple super neuron processing units in an artificial nervous system, wherein a plurality of artificial neurons is assigned to each super neuron processing unit. The super neuron processing units can be interfaced with a memory for storing and loading synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access.