Super Resolution Image Generating Device Multi-Output Architecture
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Solution Overview
Problem
Conventional super resolution (SR) image processing technologies face challenges in generating multiple output images for devices with different resolutions, leading to delays and reduced image quality, and inefficient processing when dealing with input images containing unimportant background or non-native images.
Innovation Solution
An SR image generating device with multi-magnification and multi-output capabilities, comprising configurable basic block pool circuits and shuffle circuits, allows for the generation of multiple SR output images with different resolutions without sacrificing quality, and includes features like cropping and sampling to enhance processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional SR model generates a single SR output image, then the processing architecture is simple, but additional scaling circuits are required for devices with different resolutions, causing delays and image quality loss
Solution Approach 1:
The patent divides the single SR output into multiple SR outputs with different magnifications (e.g., 2x, 4x, 8x) simultaneously. The SR processing architecture is segmented to produce multiple resolution versions in parallel, eliminating the need for subsequent scaling operations and reducing transmission delays to devices with different resolutions.
Solution Approach 2:
The SR processing system is designed to serve multiple functions simultaneously by generating multiple SR output images with different magnifications from a single input image. This multi-functional approach allows the system to adapt to various device resolutions without requiring additional scaling circuits, thereby reducing time loss and maintaining image quality.
2Reliability
If SR processing is performed on the entire input image including background, then complete processing is achieved, but processing efficiency decreases due to unimportant regions
Solution Approach 1:
The patent extracts and identifies the main image region from the input image, separating it from unimportant background areas. By taking out only the relevant main image portion for SR processing, the system maintains processing completeness for important regions while significantly improving processing efficiency by excluding unnecessary background areas.
Solution Approach 2:
The SR processing is applied with different quality levels to different regions of the image. The main image region receives full SR processing to ensure reliability, while background regions are either processed at lower quality or excluded entirely, thereby improving overall processing efficiency without compromising the quality of important areas.
3Adaptability or versatility
If the input image is not a native image, then diverse input formats are supported, but operation efficiency decreases without sampling
Solution Approach 1:
The patent performs sampling operations as a preliminary step before SR processing when the input image is not in native format. By pre-sampling the image to convert it to the appropriate format and resolution, the system maintains adaptability to diverse input formats while significantly improving the efficiency of subsequent convolution operations, avoiding the need to process entire non-native images.
Data Source
AI summary
A super resolution (SR) image generating device includes a receiving circuit, a first configurable basic block pool circuit, a first shuffle circuit, a second configurable basic block pool circuit, and a second shuffle circuit. The receiving circuit is arranged to receive an input image. The first configurable basic block pool circuit is arranged to configure multiple first basic blocks according to the input image for performing convolution operations, to generate multiple first operation results. The first shuffle circuit is arranged to shuffle the multiple first operation results to generate a first SR output image. The second configurable basic block pool circuit is arranged to configure multiple second basic blocks according to the input image for performing convolution operations, to generate multiple second operation results. The second shuffle circuit is arranged to shuffle the multiple second operation results to generate a second SR output image.