Super Self-Aligned Trench MOSFET Reducing Gate Charge
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional trench gate power MOSFETs face increased capacitances and charges as cell density increases, leading to higher conduction and switching power losses, which are not effectively minimized by existing manufacturing processes.
Innovation Solution
The development of a super self-aligned recessed-field-plate trench MOSFET structure with a body contact trench self-aligned to the gate and field-plate trenches, utilizing a pattern-reversal sequence and specific dielectric layers to reduce gate and gate-drain charges, and incorporating a thick or stepped gate dielectric to minimize capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If cell density is increased to reduce device area, then packing density improves, but capacitances and charges increase leading to higher power losses
Solution Approach 1:
The device is segmented into multiple cells arranged in a grid pattern, with each cell containing a trench gate structure. This segmentation allows high packing density while controlling the capacitance of each individual cell, thereby reducing total gate charge and power losses despite increased cell density
Solution Approach 2:
The trench gate structure provides localized field control at each cell boundary, with dielectric materials strategically placed to optimize the electric field distribution. This local quality control reduces parasitic capacitances between adjacent cells, enabling high density without proportional increases in power loss
2Ease of manufacture
If conventional trench gate structure is used, then manufacturing is simpler, but conduction and switching power losses are not minimized
Solution Approach 1:
Dielectric layers are deposited and patterned on the trench gate structure before final metallization, preliminarily establishing optimized electric field configurations. This preliminary action reduces both conduction and switching losses while maintaining compatibility with standard semiconductor manufacturing processes
Solution Approach 2:
The invention changes key parameters including dielectric constant values, layer thicknesses, and material compositions in the trench gate structure. These parameter optimizations reduce on-resistance and capacitance, minimizing power losses while using conventional fabrication techniques
3Loss of energy
If gate dielectric thickness is increased to reduce capacitance, then gate-source and gate-drain capacitance decrease, but manufacturing precision requirements increase
Solution Approach 1:
The gate dielectric is constructed as a composite structure with multiple layers of different materials and thicknesses. This composite approach achieves the desired capacitance reduction through material property optimization rather than relying solely on increased thickness, thereby reducing manufacturing precision requirements
Solution Approach 2:
Different dielectric materials with varying constants are used in different regions of the gate structure. This local quality variation allows capacitance optimization in critical areas while using thicker or simpler dielectrics in less critical regions, reducing overall manufacturing complexity
Data Source
AI summary
A manufacturing process and design structure for a super self-aligned trench power MOSFET. A plurality of super self-aligned trenches of different depths are formed into the body layer and epitaxial layers, preferably by using a multilayer stack of dielectric material etched to form spacers. Respective trenches contain gate conductors, body-contact conductors, and preferably a third trench containing a recessed field plate. This results in a MOSFET structure having high cell density and low gate charges and gate-drain charges.