Super-tag Mapping for Static Timing Analysis Memory Reduction
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Solution Overview
Problem
The increasing complexity of integrated circuit designs, particularly when clock re-convergence pessimism removal (CRPR) is enabled or there are a large number of exceptions, leads to significant memory and runtime bottlenecks in static timing analysis due to the storage of total path time delays and their propagation, often exceeding available physical memory.
Innovation Solution
The implementation of super-tags, which reference a set of total path delay values stored in a mapping table, reducing the memory needed for storage and computations by applying a delay modifier to referenced totals, allowing for efficient propagation of timing information without storing redundant data at each node.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If total path time delays are stored at each node with multiple tags for CRPR and exceptions, then timing analysis accuracy is improved, but memory usage increases significantly
Solution Approach 1:
The patent merges multiple tag values (different CRPR dominators, exceptions, and clocks) into a single super-tag that references a compact mapping table. Instead of storing separate tag values at each node, the super-tag consolidates these into one reference that points to a small set of unique values in the mapping table, dramatically reducing memory usage while preserving all timing analysis information.
Solution Approach 2:
The patent creates a compact copy of tag values in the form of a mapping table that stores only unique values. Rather than storing redundant copies of the same tag values at multiple nodes, the system stores each unique value once in the mapping table and uses super-tags to reference them, eliminating redundant storage while maintaining data integrity.
2Loss of information
If tagged totals are propagated forward to various endpoints, then complete timing information is obtained, but memory usage exceeds available physical memory
Solution Approach 1:
The patent merges the propagation of multiple tagged totals by using super-tags that reference a shared mapping table. When totals are propagated forward to endpoints, instead of carrying separate tag values through the propagation process, the system propagates super-tag references that point to the compact mapping table, reducing memory usage during propagation while maintaining complete timing information.
3Reliability
If multiple tags are stored for each node to handle CRPR and exceptions, then timing analysis correctness is improved, but computational overhead increases
Solution Approach 1:
The patent extracts the computational complexity from individual node operations by moving it to the mapping table structure. Instead of performing complex tag management operations at each node during propagation, the system uses simple super-tag references that point to pre-organized data in the mapping table, reducing computational overhead at runtime while maintaining timing analysis correctness.
Data Source
AI summary
A system and a method are disclosed for reducing memory used in storing totals during static timing analysis. Totals are stored at various points along paths analyzed in static timing analysis. Some totals may not be merged for reasons including differing clock re-convergence pessimism removal (CRPR) dominators, exceptions, or clocks. Totals at a point may be stored in a super-tag mapping table and replaced at the point with a super-tag. The super-tag includes a super-tag ID referencing the totals stored in the super-tag mapping table. The super-tag also includes a time delay value. The time delay value allows the super-tag ID to be reused in other super-tags at other points while still storing total time delays at the other points. Therefore, the memory used to store totals is reduced in many situations.