Super Via Interconnection Structure With Block Layer Alignment Buffer
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Solution Overview
Problem
The increasing complexity and miniaturization of semiconductor integrated circuits pose challenges in alignment accuracy for connecting metal layers, affecting manufacturing yield and product reliability due to stringent line width and spacing requirements.
Innovation Solution
An interconnection structure with a block layer in the second level and a super via structure connecting first and third conductive layers, which penetrates through the block layer, improving alignment deviations and enhancing process window, yield, and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the line width of metal layers and spacing between metal layers are reduced to achieve miniaturization, then the circuit density increases, but the alignment accuracy requirements become more stringent and manufacturing yield decreases
Solution Approach 1:
The patent divides the via structure into multiple segments: a first via portion extending from the first conductive layer to the block layer, and a second via portion extending from the block layer to the third conductive layer. This segmentation allows each portion to be formed with relaxed alignment requirements, as the block layer acts as an intermediate reference plane that is easier to align with than the closely spaced metal layers.
Solution Approach 2:
The block layer serves as an intermediary structure between the first and third conductive layers. It provides a stable reference plane for forming the via portions, decoupling the alignment requirements from the stringent metal layer spacing. The intermediary block layer absorbs alignment tolerances and prevents direct alignment errors between the first and third conductive layers.
2Reliability
If the alignment accuracy requirements are increased to maintain manufacturing yield, then the product reliability improves, but the circuit miniaturization is limited
Solution Approach 1:
By segmenting the via into two portions separated by the block layer, the patent enables independent formation of each via portion with relaxed alignment tolerances. This segmentation maintains reliability by ensuring proper electrical connection through the block layer intermediary, while allowing greater design freedom for circuit miniaturization without being constrained by tight alignment requirements.
Solution Approach 2:
The block layer intermediary structure maintains product reliability by providing a stable connection interface between conductive layers, while simultaneously enabling circuit miniaturization by removing the constraint of stringent alignment requirements. The intermediary absorbs alignment variations, allowing smaller feature sizes without compromising connection reliability.
3Reliability
If the super via structure is formed directly between first and third conductive layers, then the interconnection is achieved, but alignment deviations cause negative influences on manufacturing yield
Solution Approach 1:
The patent segments the super via structure into a first via portion and a second via portion, with the block layer serving as an intermediate connection point. This segmentation allows each via portion to be formed independently with relaxed alignment requirements, reducing the impact of alignment deviations and improving manufacturing yield while maintaining interconnection reliability.
Solution Approach 2:
The block layer acts as an intermediary that decouples the alignment requirements between the first and third conductive layers. By forming vias to the block layer intermediary rather than directly between the metal layers, alignment deviations have reduced negative influence, thereby improving manufacturing yield while maintaining reliable interconnection.
Data Source
AI summary
An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.