Capacitively Coupled Superconducting Circuits for Low-Power AC Clocking
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Solution Overview
Problem
CMOS technology-based digital circuits face limitations in device size and power consumption, especially at high clock speeds, due to static power dissipation and current leakage even when inactive, leading to inefficiencies in high-performance digital systems.
Innovation Solution
The use of superconducting integrated circuits with capacitive coupling and Josephson junctions, powered by alternating current (AC), which eliminates static power dissipation and current leakage, enabling low-power operation and efficient data encoding through single-flux-quantum (SFQ) pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CMOS circuits are used to achieve high clock speeds, then processing performance is improved, but power consumption increases due to static power dissipation and current leakage
Solution Approach 1:
The patent transitions from CMOS technology operating at DC voltage to superconducting logic circuits operating with AC clock signals. This fundamental parameter change eliminates static power dissipation and current leakage while enabling high-speed operation through Josephson junctions that switch at GHz frequencies without resistive losses.
Solution Approach 2:
The patent replaces the electronic switching mechanism of CMOS transistors with quantum-mechanical Josephson junctions. These junctions utilize quantum tunneling effects to achieve lossless switching, substituting the resistive switching mechanism of CMOS with a superconducting quantum effect that dissipates no energy during state transitions.
2Reliability
If CMOS circuits are used to maintain transistor state, then circuit functionality is preserved, but power is continuously consumed even when inactive
Solution Approach 1:
The patent employs AC clock signals that periodically drive the superconducting circuits through defined phases. During inactive periods, the circuits naturally maintain their quantum states without requiring continuous power input. The periodic AC excitation only activates the circuits when computation is required, eliminating continuous static power dissipation while preserving functional reliability.
3Area of moving object
If device size is reduced in CMOS technology, then integration density is improved, but power leakage increases and device limits are reached
Solution Approach 1:
The patent changes the fundamental operating parameters from DC-biased CMOS to AC-driven superconducting circuits. Josephson junctions can be fabricated with comparable or smaller dimensions than CMOS transistors but operate without the leakage currents that plague scaled CMOS devices. The superconducting state eliminates resistive losses entirely, allowing continued miniaturization without encountering the power leakage walls that limit CMOS scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in zero static power dissipation, reduced energy dissipation at high frequencies, and supports low-latency, high-performance digital circuits with scalable feature sizes, improving efficiency and reducing fabrication complexity.
Implementation Method 1
a first clock line coupled via a first capacitor to a first superconducting circuit comprising a first Josephson junction, where the first capacitor is configured to receive a first clock signal having a first phase and couple a first bias current to the first superconducting circuit
Implementation Method 2
a first superconducting circuit comprising a first Josephson junction
Data Source
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AI summary
Capacitively coupled superconducting integrated circuits powered using alternating current clock signals are described. An example superconducting integrated circuit includes a first clock line coupled via a first capacitor to a first superconducting circuit including a first Josephson junction, where the first capacitor is configured to receive a first clock signal having a first phase and couple a first bias current to the first superconducting circuit. The superconducting integrated circuit further includes a second clock line coupled via a second capacitor to a second superconducting circuit including a second Josephson junction, where the second capacitor is configured to receive a second clock signal having a second phase and couple a second bias current to the second superconducting circuit, and where the second phase is different from the first phase.