Superconducting Multi-Row Circuit Layout for Timing and Placement Flexibility
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Solution Overview
Problem
Existing superconducting electronics (SCE) designs face challenges in ensuring precise timing between logic gates while providing placement and routing flexibility, which is crucial for meeting design constraints and improving the quality of results in place-and-route systems.
Innovation Solution
A parameterized superconducting multi-row circuit is introduced, where sub-blocks are clocked using different phases, and their relative locations are determined based on parameter values, allowing for flexible placement and routing without compromising precise timing, using technologies like AQFP, QFP, DSFQ, and RQL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sub-blocks are placed with fixed relative locations to ensure precise timing, then timing precision is improved, but placement flexibility is worsened
Solution Approach 1:
The patent applies dynamics by making the relative locations of sub-blocks adjustable rather than fixed. Parameter values can be modified to change the spacing and positioning of sub-blocks along the second direction, allowing the circuit to adapt its physical layout while maintaining timing precision through corresponding adjustments in timing compensation values.
Solution Approach 2:
The patent changes parameters by introducing a set of parameter values that determine the relative locations of sub-blocks. By modifying these parameter values, the physical configuration of the circuit can be adjusted without compromising timing precision, as the timing model is updated with corresponding compensation values.
2Adaptability or versatility
If parameterized placement is used to improve placement flexibility, then placement flexibility is improved, but timing precision is worsened
Solution Approach 1:
The patent implements feedback through the timing model that computes timing compensation values based on the actual parameter values used in placement. This feedback mechanism ensures that even when sub-block locations are adjusted for flexibility, the timing precision is restored by compensating for the changes in relative positions and connection lengths.
Solution Approach 2:
The patent applies preliminary action by pre-computing timing compensation values for different parameter configurations. This allows the timing model to quickly adjust for placement changes without requiring complex real-time calculations, maintaining timing precision while enabling flexible placement.
3Adaptability or versatility
If connection lengths are resized based on parameter values to enable flexible routing, then routing flexibility is improved, but timing control is worsened
Solution Approach 1:
The patent makes the connection lengths dynamic by resizing them based on parameter values. The timing model adapts to these changes by computing compensation values that account for the varying connection lengths, ensuring timing control is maintained despite the flexibility in routing.
Solution Approach 2:
The patent changes the parameters governing connection lengths to enable flexible routing. By adjusting parameter values, the physical length of connections between sub-blocks can be modified, and the timing model compensates for these changes to maintain reliable timing control.
Data Source
AI summary
A parameterized superconducting circuit may include a set of sub-blocks which include superconducting circuitry. Different sub-blocks in the set of sub-blocks may be clocked using clock signals having different phases. Along a first direction, relative locations of the set of sub-blocks may be fixed. Along a second direction, relative locations of the set of sub-blocks may be determined based on a set of parameter values.