Superconducting C-Coupler for Transmon Qubits
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Solution Overview
Problem
The challenge in fabricating semiconductor devices for quantum computing is the limited space on the fabrication plane due to the large size of capacitive coupling structures, which restricts the number of qubits that can be fabricated per die, necessitating a method to couple readout circuitry with superconducting quantum logic circuits without occupying the same plane as the Josephson junction and its driving capacitors.
Innovation Solution
The implementation of a superconducting capacitive coupling device, known as a superconducting C-coupler, which is fabricated through a silicon substrate using a partial via structure that protrudes from the backside, allowing capacitive coupling between qubit elements and readout circuitry while freeing up space on the frontside for additional qubits, and optionally includes dielectric material filling or air-filled trenches for reduced interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitive coupling structures are fabricated coplanar with qubit elements, then electrical coupling is achieved, but fabrication space is consumed limiting qubit density
Solution Approach 1:
The patent transitions from coplanar coupling to three-dimensional vertical coupling by fabricating capacitive coupling structures that extend through the substrate thickness. The first capacitive coupling structure is formed on the front surface while the second capacitive coupling structure extends vertically to the back surface, enabling electrical coupling without occupying additional planar fabrication space.
Solution Approach 2:
The capacitive coupling structures are nested within the substrate volume rather than occupying surface area. The structures are embedded in the substrate thickness, with conductive regions positioned at different depths and surfaces, effectively utilizing the third dimension (z-axis) for coupling functionality.
2Device complexity
If readout circuitry is placed on the same plane as qubit elements, then coupling is simplified, but qubit density is reduced
Solution Approach 1:
The patent separates readout circuitry from qubit elements by placing them on opposite surfaces of the substrate. Qubit elements are fabricated on the front surface while readout circuitry is fabricated on the back surface, with capacitive coupling structures extending vertically through the substrate to bridge the two surfaces, thereby increasing qubit density on the front surface while maintaining coupling functionality.
3Ease of manufacture
If coplanar capacitive coupling is used, then fabrication process is simple, but space for additional qubits is limited
Solution Approach 1:
The patent employs vertical stacking of capacitive coupling structures that extend through the substrate thickness, utilizing the z-dimension for coupling functionality. This approach maintains fabrication process simplicity by using standard semiconductor manufacturing techniques while freeing up planar fabrication space for additional qubit elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient capacitive coupling between qubit elements and readout circuitry without occupying valuable space on the qubit device plane, allowing for increased qubit density and flexible placement of readout circuitry on the backside, thereby enhancing the fabrication efficiency and scalability of quantum computing devices.
Implementation Method 1
A via layer comprising a superconducting material is deposited in the trench... the via layer capacitively coupled with the superconducting pad
Implementation Method 2
A via layer comprising a superconducting material is deposited in the trench... An extension of the via layer is on the backside, wherein the extension couples to a quantum readout circuit element
Data Source
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AI summary
A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.