Superconducting Edge-Triggered Latches for Zero Static Power Dissipation
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Solution Overview
Problem
CMOS technology-based digital circuits face limitations in device size and power consumption, particularly due to static power dissipation and current leakage even when inactive, leading to inefficiencies in high-performance digital systems.
Innovation Solution
The implementation of superconducting logic circuits using Josephson junctions and AC power, which eliminates static power dissipation and current leakage by employing edge-triggered latches and edge detect circuits to manage data latching with zero static power dissipation and alternating current power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If CMOS technology is used for digital circuits, then device functionality and integration are achieved, but static power dissipation and current leakage occur even when circuits are inactive
Solution Approach 1:
The patent employs periodic AC power supply at specific frequencies to control superconducting Josephson junctions, creating time-dependent switching behavior. The AC power is applied in synchronized phases to master and slave latches, enabling periodic data transfer only during specific clock cycles, thereby eliminating static power while maintaining reliable data latching through timed periodic action
Solution Approach 2:
The patent changes the fundamental operating parameter from DC voltage (CMOS) to AC power at specific frequencies (superconducting logic). By using AC power supplied to bias teardrops and Josephson junctions, the system achieves zero static power dissipation while the frequency and phase parameters of the AC signal control the timing and reliability of data latching operations
2Loss of energy
If DC voltage is used to power CMOS circuits, then continuous operation is maintained, but current leakage occurs even when circuits are inactive
Solution Approach 1:
The patent replaces continuous DC power with periodic AC power supply that is synchronized to clock signals. Power is delivered in periodic pulses during specific phases of the AC cycle, enabling data processing operations only when power is actively supplied. This periodic power delivery eliminates continuous current leakage while maintaining data processing throughput through synchronized periodic operation of logic circuits
Solution Approach 2:
The patent extracts the harmful continuous DC power component and replaces it with discrete AC power pulses delivered only when needed for logic operations. By taking out the continuous power supply and replacing it with periodic AC power synchronized to data processing needs, the system eliminates current leakage while preserving productivity through on-demand power delivery during active processing phases
3Loss of energy
If superconducting logic circuits are used, then static power dissipation is eliminated, but device complexity increases due to Josephson junctions and AC power requirements
Solution Approach 1:
The patent implements master and slave latches that serve multiple functions: they act as data storage elements, clocked by AC power synchronized signals, and simultaneously function as power management components. The AC power bias teardrops serve both to provide operating bias to Josephson junctions and to transfer data between latches, reducing overall system complexity despite the sophisticated superconducting logic elements
Solution Approach 2:
The patent merges the power supply function with the data transfer function by using AC power-supplied bias teardrops that simultaneously provide operating power to Josephson junctions and transfer data signals between master and slave latches. This merging of power delivery and data signaling functions reduces the number of separate components needed, offsetting the increased complexity of superconducting logic elements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables low-power operation with zero static power dissipation and efficient data latching, allowing for the mapping of CMOS technology-based designs to superconducting logic-based designs, reducing power consumption and improving performance.
Implementation Method 1
The implementation of superconducting logic circuits using Josephson junctions and AC power, which eliminates static power dissipation and current leakage
Data Source
AI summary
Superconducting circuits and methods for latching data are described. An example superconducting circuit includes an edge detect circuit configured to receive a logical clock signal and generate a return-to-zero clock signal. The superconducting circuit further includes a first latch configured to receive the logical clock signal and an input data signal, where the first latch is further configured to selectively delay the input data signal to generate a delayed data signal. The superconducting circuit further includes a second latch configured to receive the return-to-zero clock signal and the delayed data signal, where the second latch is further configured to capture a logical high value corresponding to the input data signal in response to a rising edge of the return-to-zero clock signal and capture a low logical value corresponding to the input data signal in response to a falling edge of the return-to-zero clock signal.