Superconducting IC Fabrication with Stud Vias and Low-Noise Layer Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The fabrication of superconducting integrated circuits faces challenges due to contamination issues and the need for specialized processes, which are not easily transferrable from semiconductor fabrication, leading to noise and inefficiencies in qubit functionality.
Innovation Solution
A method involving the deposition and patterning of superconducting metal layers, kinetic inductance layers, and dielectric layers to form a superconducting integrated circuit with specific structures such as stud vias and capacitors, using materials like niobium and titanium nitride, and employing techniques like chemical mechanical planarization and dual masks to optimize layer alignment and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If superconducting integrated circuits are fabricated using traditional semiconductor fabrication facilities, then manufacturing cost and accessibility are improved, but contamination occurs and manufacturing precision deteriorates
Solution Approach 1:
The fabrication process is segmented into two distinct environments: semiconductor fabrication facilities for initial processing steps, and specialized superconducting fabrication facilities for critical superconducting layer processing. This segmentation allows each facility to be optimized for its specific requirements, preventing contamination while maintaining manufacturing accessibility.
Solution Approach 2:
Transfer substrates serve as intermediaries between semiconductor and superconducting fabrication facilities. The substrates are processed at semiconductor facilities, then transferred to superconducting facilities for final processing. This intermediary mechanism enables process transferability while preventing cross-contamination between the two fabrication environments.
2Manufacturing precision
If specialized superconducting fabrication processes are used, then manufacturing precision and coherence are improved, but device complexity and process difficulty increase
Solution Approach 1:
The fabrication process utilizes universal process modules that can be applied across different superconducting circuit designs. Standardized deposition, patterning, and planarization techniques are developed that work across multiple device types, reducing process complexity while maintaining high manufacturing precision for quantum computing applications.
3Reliability
If gold is used as a resistor material in superconducting circuits, then electrical performance is improved, but contamination of semiconductor facilities occurs
Solution Approach 1:
The gold resistor fabrication step is extracted from the semiconductor fabrication process and relocated to the specialized superconducting fabrication facility. This extraction eliminates the contamination source from semiconductor facilities while preserving the electrical performance benefits of gold resistors in the final superconducting circuits.
4Adaptability or versatility
If multiple superconducting metal layers are deposited and patterned, then circuit functionality and integration are improved, but manufacturing precision requirements and noise increase
Solution Approach 1:
Chemical mechanical planarization is performed as a preliminary action between deposition and patterning steps to ensure each layer starts with a perfectly flat surface. This preliminary planarization prevents cumulative alignment errors and reduces noise, enabling high-precision fabrication of multi-layer superconducting circuits with complex functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-quality superconducting integrated circuits with reduced noise and improved coherence times, suitable for quantum computing applications by addressing contamination and process transferability issues.
Implementation Method 1
a kinetic inductance layer overlying at least one of the plurality of superconducting stud vias, wherein the kinetic inductance layer includes a material superconductive in a respective range of temperatures, the material which causes a larger proportion of energy stored in the kinetic inductance layer to be stored as kinetic inductance than magnetic inductance
Data Source
AI summary
Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.