Superconducting Qubit Backside Etching to Reduce Interface RF Loss
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Solution Overview
Problem
Existing methods for improving qubit lifetime and coherence time in superconducting quantum computing systems, such as front side etching, disrupt qubit performance and are limited by RF losses at material interfaces, particularly silicon-air, silicon-metal, and metal-air interfaces.
Innovation Solution
A method involving backside etching of the substrate to reduce RF losses by modifying the overlap with different material interfaces, including trenches and superconducting metal layers to enhance qubit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If front side etching is used to reduce surface states and RF losses, then qubit lifetime and coherence time are improved, but the qubit performance is significantly perturbed due to strong electromagnetic field strengths in the etched region
Solution Approach 1:
The patent inverts the conventional approach by performing etching on the backside of the substrate rather than the front side. This allows modification of the substrate to reduce RF losses while keeping the qubit structure on the front side intact and unperturbed, thereby maintaining qubit performance stability while still achieving improved coherence time
Solution Approach 2:
The patent moves the etching operation from the front side (where the qubit resides) to the backside of the substrate, effectively using the third dimension (substrate thickness) to separate the modification zone from the qubit zone. This dimensional shift allows RF loss reduction without direct interference with the qubit's electromagnetic field
2Duration of action of stationary object
If front side etching is performed after chip fabrication, then surface states can be reduced, but the chip must be de-bonded to perform further processing which complicates manufacturing
Solution Approach 1:
The patent performs the etching operation on the backside of the substrate before the chip is flip chip bump bonded. This preliminary action allows the substrate to be modified while still in a accessible state, and the etched features then serve their function of reducing RF losses after the chip is assembled, eliminating the need for de-bonding
Solution Approach 2:
By inverting the etching location to the backside, the patent enables manufacturing-friendly processing timing - the etching can be done early in the fabrication sequence before bonding operations, whereas front-side etching would require post-assembly intervention
3Ease of manufacture
If the bump bonding process is used to assemble the chip, then the qubit structure can be formed, but the bump bonding process itself influences final qubit performance metrics negatively
Solution Approach 1:
The patent applies preliminary anti-action by etching the backside of the substrate to reduce RF losses before the bump bonding process occurs. This pre-compensation for potential losses ensures that even after bump bonding, the qubit maintains optimal coherence time, effectively counteracting the negative influence of the bonding process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly improves qubit lifetime (T1) and coherence time (T2) by reducing RF losses through strategic etching and metallization, optimizing RF energy distribution across various interfaces.
Implementation Method 1
removing an amount of substrate material from the backside of the substrate at an area opposite the at least one qubit to reduce radiofrequency electrical current loss due to at least one of silicon-air (SA) interface, metal-air (MA) interface or silicon-metal (SM) interface
Implementation Method 2
The drastic change in the device geometry affects both the dielectric and flux noise environment experienced by the qubit. In particular, the participation ratios of various dielectric interfaces are significantly modified
Data Source
Figure 1A~1C
Figure 2~3
Figure 4A~4B
AI summary
A method for improving lifetime and coherence time of a qubit in a quantum mechanical device includes providing a substrate having at least one qubit formed on the frontside, the at least one qubit having capacitor pads, and removing substrate material from the backside at an area opposite the qubit and/or depositing a superconducting metal layer at the backside area opposite the qubit to reduce radiofrequency electrical current loss due to at least one of silicon-air (SA) interface, metal-air (MA) interface or silicon-metal (SM) interface.