Superconducting Qubit Circuit Layout for SQUID Coupling and Q-Value
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Solution Overview
Problem
Existing superconducting quantum circuit designs face a trade-off between magnetic field coupling strength and internal Q-value, making it difficult to achieve both simultaneously due to high capacitance between the SQUID loop and coil wiring when chips are closely spaced.
Innovation Solution
A superconducting quantum circuit apparatus is designed with a first chip having a SQUID loop and a second chip with a wiring layer, where the second chip's wiring layer includes an opening juxtaposed with the SQUID loop and extends to a ground pattern, allowing for increased distance and reduced capacitance while maintaining magnetic field coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the first chip and the second chip are narrow spaced to strengthen magnetic field coupling, then the magnetic field coupling strength is improved, but the capacitance between the SQUID loop and coil wiring increases, degrading the internal Q-value
Solution Approach 1:
The patent introduces a via hole structure that extends vertically through the substrate, transforming a planar capacitance problem into a three-dimensional solution. The via hole provides a vertical current return path that separates the magnetic coupling function from the capacitive coupling, allowing strong magnetic field coupling while maintaining low capacitance by utilizing the third dimension (depth) rather than increasing planar separation.
Solution Approach 2:
The via hole acts as an intermediary structure that mediates between the coil wiring on the first chip and the ground reference on the second chip. It provides a controlled impedance path for return current that prevents unwanted capacitive coupling while allowing the magnetic field to penetrate through the opening in the ground pattern, thus decoupling the magnetic interaction from the electrical capacitance.
2Reliability
If the distance between chips is increased to reduce capacitance, then the internal Q-value is improved, but the magnetic field coupling strength decreases
Solution Approach 1:
By introducing vertical via holes that extend through the substrate thickness, the patent enables strong magnetic coupling without requiring close planar spacing. The via holes provide a three-dimensional current path that maintains electromagnetic coupling efficiency while allowing increased horizontal separation between the SQUID loop and coil wiring, thus improving Q-value without sacrificing coupling strength.
Solution Approach 2:
The patent changes the geometric parameters of the wiring structure by introducing via holes with specific dimensions and positioning them at critical locations. This parameter change transforms the current distribution and magnetic field configuration, enabling the system to achieve both strong coupling and high Q-value by optimizing the via hole diameter, depth, and position rather than simply adjusting chip spacing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design secures a strong magnetic field coupling and ensures a desired internal Q-value, improving the performance of the qubit circuit by minimizing unintended capacitance and signal interference.
Implementation Method 1
a nonlinear inductor, such as a superconducting quantum interference device (SQUID) which includes multiple Josephson junctions in a loop
Implementation Method 2
a superconducting quantum interference device (SQUID) which includes multiple Josephson junctions in a loop
Implementation Method 3
a second chip with a coil wiring (current path for applying a magnetic field) configured to generate a magnetic field
Data Source
AI summary
Provided a first chip including a qubit circuit including a SQUID in a wiring layer formed on a substrate of the first chip; and a second chip including a wiring layer on a first side of a substrate of the second chip, the wiring layer on the first side disposed opposed to the wiring layer of the first chip, the wiring layer of the first chip including an opening juxtaposed with the SQUID, the wiring layer on the first side of the second chip including a first wiring having one end connected to a terminal, and in a region opposite at least the opening of the first chip, being extended along the qubit circuit of the first chip, the first wiring having other end connected to a ground pattern arranged in the wiring layer on the first side of the second chip.