Superconducting RQL Circuits for Low-Power SFQ Logic Gating

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Solution Overview

Problem

CMOS technology-based digital circuits face limitations in device size and power consumption, particularly due to static power dissipation and current leakage even when inactive, leading to inefficiencies in high-performance digital systems.

Innovation Solution

The implementation of superconducting circuits using Josephson junctions and alternating current (AC) power, which enables the creation of low-power reciprocal quantum logic (RQL) circuits that pass single-flux-quantum (SFQ) pulses, eliminating static power dissipation and using fewer components for logic operations, such as XOR gates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If CMOS technology is used for digital circuits, then device functionality and integration are achieved, but power consumption increases due to static power dissipation and current leakage

Engineering Contradiction:
Improvepower consumptionVSAvoiddevice functionality
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent transitions from CMOS technology operating at room temperature to superconducting circuits operating at cryogenic temperatures (e.g., 4K or lower), fundamentally changing the thermal parameter to eliminate resistive power loss and enable lossless signal transmission through superconducting materials

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the voltage-based CMOS logic system with a current-based superconducting logic system using Single Flux Quantum (SFQ) pulses and Josephson junctions, substituting the electrical field mechanism with a quantum mechanical tunneling mechanism that operates without resistive dissipation

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If CMOS circuits operate at high clock speeds, then processing performance improves, but power consumption increases due to dynamic and static power loss

Engineering Contradiction:
Improveprocessing performanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent employs periodic clocking schemes where superconducting circuits are activated only during specific clock phases to process signals, allowing the system to maintain high processing performance while consuming power only during active computation windows rather than continuously

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent changes the operational temperature parameter to cryogenic levels, enabling superconducting materials to carry current without resistance, thereby allowing high-speed operation without the proportional increase in power consumption that plagues CMOS systems

Inventive Principle:
Principle #35Parameter changes

3Area of moving object

If device size is reduced in CMOS technology, then integration density improves, but power loss from maintaining transistor state increases

Engineering Contradiction:
Improvedevice sizeVSAvoidpower loss
Core Design Contradiction:
Area of moving objectVSLoss of energy

Solution Approach 1:

The patent replaces voltage-threshold-based CMOS transistor switching with Josephson junction-based SFQ pulse generation, where logic states are represented by quantized magnetic flux packets rather than voltage levels, eliminating the need for continuous power to maintain state in miniaturized devices

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent transitions from room-temperature operation with high leakage currents to cryogenic operation with superconducting materials, where the fundamental change in electrical resistance parameter enables high-density integration without proportional increases in power loss

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in reduced power consumption, higher density fabrication, and faster logic operations without the need for high-efficiency gate transformers, addressing the inefficiencies of CMOS technology.

Implementation Method 1

The implementation of superconducting circuits using Josephson junctions and alternating current (AC) power, which enables the creation of low-power reciprocal quantum logic (RQL) circuits that pass single-flux-quantum (SFQ) pulses

Methodology Applied
Scientific EffectJosephson effect: Josephson Effect

Implementation Method 2

The consumption of power is partly the result of power loss from the dissipation of energy even when the CMOS circuits are inactive... An alternative approach to the use of processors and related components based on CMOS technology is the use of superconducting circuits based devices

Methodology Applied
Scientific EffectSuperconductivity: Superconductivity

Data Source

PatentUS10411713B2Superconducting circuits based devices and methods
Publication Date: 2019.09.10 NORTHROP GRUMMAN SYSTEMS CORP
  • US10411713B2 patent drawing
  • US10411713B2 patent drawing
  • US10411713B2 patent drawing

AI summary

Superconducting circuits based devices and methods, including reciprocal quantum logic (RQL) based devices and methods are provided. In one example, a device comprising an output terminal, a first input terminal for receiving a first set of pulses, and a second input terminal for receiving a second set of pulses is provided. The first section may be configured to pass a single pulse received during a single clock cycle at any of the first input terminal or the second input terminal, but to not pass two or more positive pulses received during a single clock cycle at the first input terminal and the second input terminal. The second section, coupled to the first section, may be configured to, in response to the single pulse, generate a negative pulse after a predetermined fraction of a single clock cycle after providing a positive pulse at the output terminal.