Superconductive Interconnect Layout for Shallow Low-Inductance Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing superconducting interconnect structures face limitations in downsizing and require techniques that allow for high-density routing with tight cross-section control, especially for high-kinetic inductance materials like NbTiN, while minimizing parasitic inductance and achieving shallow vias.
Innovation Solution
A method involving a combination of metal etch and damascene-type processes to form superconducting interconnect structures, including forming a first entity with superconductive and dielectric layers, patterning via holes, and filling them with superconductive materials to achieve tight control over pitch and cross-section.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If metal etch is used to form superconducting interconnects, then the process is suitable for many superconducting materials, but the possibility for downsizing interconnect structures is limited
Solution Approach 1:
The patent divides the interconnect formation into separate stages: first forming the superconductive layer, then creating dielectric layers with embedded via holes, and finally filling the via holes with superconductive material. This segmentation allows precise control of each component's dimensions, enabling downsizing while maintaining material compatibility.
Solution Approach 2:
The patent transitions from planar metal etch to a three-dimensional damascene approach where via holes are formed through dielectric layers and filled with superconductive material. This dimensional change enables better control over interconnect geometry and size reduction.
2Ease of manufacture
If conventional Nb wires are used, then they can be fabricated with existing processes, but they have high sensitivity to parasitic and magnetic coupling requiring multiple ground planes
Solution Approach 1:
The patent uses high-kinetic inductance superconductive materials specifically in the interconnect regions where magnetic coupling sensitivity is critical, while maintaining compatibility with existing fabrication processes. This localized application of specialized materials reduces parasitic effects without requiring multiple ground planes.
3Object-affected harmful factors
If high-kinetic inductance material is used, then low sensitivity to parasitic magnetic coupling is achieved, but tight control of material parameter spread throughout fabrication is required
Solution Approach 1:
The patent forms the superconductive layer and dielectric layers with embedded via hole patterns before final superconductive filling. This preliminary structuring with controlled geometry allows subsequent superconductive material deposition to achieve tight parameter control, as the physical constraints of the pre-formed structures limit material parameter variation.
Solution Approach 2:
The patent controls material parameter spread by changing the fabrication approach from direct metal etch to damascene processing, where the via hole geometry (width, depth, aspect ratio) serves as a physical template that constrains and standardizes the superconductive material properties throughout the structure.
4Productivity
If superconducting interconnect structures are downsized, then high density routing is enabled, but the cross-section control becomes more difficult
Solution Approach 1:
The patent controls cross-section dimensions by transitioning to a vertical via-hole filling approach rather than planar etching. The via hole geometry (width, depth, aspect ratio) is precisely controlled during dielectric layer formation, and this three-dimensional template ensures tight cross-section control even as structures are downsized for high-density routing.
5Object-affected harmful factors
If shallow vias are formed, then low parasitic inductance is achieved, but the aspect ratio control becomes more challenging
Solution Approach 1:
The patent forms dielectric layers with embedded via hole patterns before superconductive filling, allowing preliminary control of via hole depth and width. By establishing the via hole geometry early in the process with controlled aspect ratios, the subsequent superconductive filling naturally produces shallow vias with low parasitic inductance while maintaining precise aspect ratio control.
Data Source
AI summary
A method for forming a superconducting interconnect structure, comprising: providing a substrate, forming a superconductive layer, forming a layer of a first dielectric material, removing parts of the layer of the first dielectric material and of the superconductive layer so as to form a pattern comprising a first set of line structures comprising: a first set of superconductive line structures, and a first set of line structures made of the first dielectric material, forming a second dielectric material between the line structures of the first set, forming a layer formed of a third dielectric material, providing a patterned mask, transferring the pattern into the first dielectric material and into the layer formed of the third dielectric material, so as to form the at least one via hole, removing the patterned mask, and forming a superconductive material layer so as to form at least one via.