Superconductor Interconnect Preclean for Oxide-Free Dual Damascene

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Solution Overview

Problem

The fabrication of superconducting circuits faces challenges in achieving consistent and rapid production due to oxidation of conductive contacts and lines during the chemical mechanical polishing process, which degrades performance, and existing methods like argon sputter etching can cause redeposition of non-volatile superconducting compounds.

Innovation Solution

A preclean process using a tetrafluoromethane (CF4) based plasma clean etch is integrated into the dual damascene process, where oxygen is initially flowed with CF4 to increase fluorine radicals for oxide removal, and then CF4 alone is used to finish the etch, ensuring a smooth surface before dielectric deposition, effectively removing unintentional oxidation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If argon sputter etch process is used to remove oxidized layers, then oxide removal is achieved, but non-volatile superconducting compounds are redeposited on substrate surface

Engineering Contradiction:
Improveoxide removal qualityVSAvoidredeposition of non-volatile compounds
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent changes the chemical parameters of the etch process by using CF4-based plasma instead of argon sputter etching. This chemical etching approach removes oxides through fluorine radical reactions without causing redeposition of superconducting compounds, fundamentally changing the removal mechanism from physical sputtering to chemical reaction.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a disposable-like approach by using a dedicated preclean etch step with CF4 plasma that is specifically designed to remove oxides without creating persistent contamination. The process uses a controlled chemical reaction that leaves no redeposited material, effectively treating the etch as a single-use cleaning operation.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Ease of manufacture

If dual damascene process is used for superconducting circuit fabrication, then interconnect structure is formed, but oxidation of conductive contacts and lines occurs during CMP and oxygen exposure

Engineering Contradiction:
Improveinterconnect formation capabilityVSAvoidconductive contact integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies a preclean etch process immediately after CMP and before dielectric deposition, creating a protective action that removes oxides formed during CMP and oxygen exposure. This preliminary cleaning step ensures the superconducting contacts are oxide-free before the next processing step, preventing performance degradation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses CF4-based plasma which creates a fluorinated environment that prevents oxidation. The fluorine radicals react with and remove oxygen-containing species from the superconducting surface, effectively creating an inert chemical environment that protects the conductive contacts from further oxidation during subsequent processing.

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

3Productivity

If CF4 based plasma clean etch is used with oxygen flow, then oxide removal rate increases, but potential for over-etching or surface damage increases

Engineering Contradiction:
Improveoxide removal rateVSAvoidsurface integrity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent employs a two-stage periodic etch process: first stage with CF4 and O2 flow for rapid oxide removal, second stage with CF4 only for surface smoothing and termination. This periodic switching between aggressive cleaning and gentle finishing modes achieves both high removal rate and surface integrity.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent uses excessive oxygen flow temporarily during the first stage to ensure complete oxide removal, then stops oxygen flow for the second stage to prevent over-etching. The controlled excess of reactive species in the first stage is followed by a termination stage that stops the aggressive reaction, achieving complete oxide removal without surface damage.

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method ensures a smooth, oxidation-free surface for superconducting interconnects, enhancing the reliability and performance of superconducting circuits by preventing redeposition of non-volatile compounds and maintaining the integrity of the metal interconnects.

Implementation Method 1

A preclean process is performed on the superconducting metal interconnect elements. The preclean process employs a tetrafluoromethane (CF4) based plasma clean etch process

Methodology Applied
Scientific EffectPlasma etching: Plasma

Implementation Method 2

The CF4 will combine with the metal-oxide to form a gas that will evaporate off the surface of the superconducting interconnect element

Methodology Applied
Scientific EffectChemical reaction forming volatile compounds: Chemical Bonding

Implementation Method 3

oxygen is initially flowed with CF4 to increase fluorine radicals for oxide removal

Methodology Applied
Scientific EffectRadical generation: Ionisation

Implementation Method 4

effectively removing unintentional oxidation

Methodology Applied
Scientific EffectOxidation prevention: Oxidation

Data Source

PatentEP3501032B1Preclean methodology for superconductor interconnect fabrication
Publication Date: 2023.10.18 NORTHROP GRUMMAN SYSTEMS CORP
  • EP3501032B1 patent drawingFigure 1~2
  • EP3501032B1 patent drawingFigure 3~4
  • EP3501032B1 patent drawingFigure 5~6

AI summary

A method is provided of forming a superconductor device interconnect structure. The method includes forming a first dielectric layer overlying a substrate, and forming a superconducting interconnect element in a first dielectric layer, such that the superconducting interconnect element has a top surface aligned with a top surface of the first dielectric layer to form a first interconnect layer. The method also includes performing a plasma clean on a top surface of the first interconnect layer, and depositing a second dielectric layer over the first dielectric layer.