Superjunction MOSFET Bias Clamping for Lower Reverse Recovery Loss
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Solution Overview
Problem
Superjunction transistor devices experience significant losses during the transition from a diode state to a blocking state due to the reverse recovery current, which affects both the transistor itself and connected devices.
Innovation Solution
Applying a bias voltage between the bias region and either the compensation region or the body region, or both, to reverse bias the pn-junctions, thereby reducing the losses associated with removing charge carriers and charging the junction capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the MOSFET operates in diode state with forward biased body diode, then current conduction is enabled, but significant commutation losses occur during transition to blocking state due to reverse recovery current
Solution Approach 1:
The patent applies preliminary anti-action by using a bias voltage source to pre-bias the pn-junctions in the drift and body regions before the MOSFET transitions from diode state to blocking state. This pre-biasing creates an opposing electric field that counteracts the reverse recovery current, thereby reducing commutation losses during the state transition.
Solution Approach 2:
The patent implements preliminary action by提前 applying a bias voltage to the pn-junctions before the actual state transition occurs. This preliminary biasing prepares the junctions to handle the transition more efficiently, reducing the reverse recovery current and associated losses when the MOSFET switches from diode conduction to blocking state.
2Loss of energy
If bias voltage is applied to reverse bias pn-junctions, then commutation losses are reduced, but additional circuit components and complexity are introduced
Solution Approach 1:
The patent achieves multi-functionality by designing the bias voltage source to serve multiple purposes: it pre-biases the pn-junctions to reduce commutation losses, and also shapes the voltage waveform during state transitions. This universal approach reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall device complexity.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the bias voltage level based on the operating state of the MOSFET. The bias voltage is applied only during critical transition periods and adjusted according to the specific transition requirements, rather than maintaining a constant high bias level. This selective parameter adjustment reduces losses while minimizing the impact on circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the commutation losses by managing the charge carrier plasma and junction capacitance expansion, improving the efficiency of the transition process.
Implementation Method 1
Applying a bias voltage between the bias region and either the compensation region or the body region, or both, to reverse bias the pn-junctions
Implementation Method 2
charging the junction capacitance
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
A transistor arrangement is disclosed. The transistor arrangement includes: a superjunction transistor device (TSJ) comprising a source node (S), a gate node (G), a drain node (D) and a bias node (Q); a bias voltage source (VSDEP) configured to provide a bias voltage (VDEP) and an electronic switch (SWDEP) configured to couple the bias voltage source (VSDEP) between the bias node (Q) and a further bias node (R); and a clamping circuit (92) coupled between the bias node (Q) and the source node (S) and configured to clamp a voltage between the bias node (Q) and the further bias node (R) to a clamping voltage level.