Superjunction Transistor Biasing for Reverse Recovery Loss Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Superjunction transistor devices experience significant losses during the transition from a diode state to a blocking state due to the reverse recovery current, which affects both the transistor itself and connected devices.

Innovation Solution

The introduction of a bias voltage applied between the bias region and at least one of the compensation region and the body region, with the bias voltage being different from zero, helps to reverse bias the pn-junctions, thereby reducing the losses associated with removing charge carriers and charging the junction capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the superjunction transistor device operates in diode state and then transitions to blocking state, then the device can perform normal switching operations, but significant commutation losses occur due to reverse recovery current

Engineering Contradiction:
Improveswitching operation capabilityVSAvoidcommutation losses
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies preliminary action by reverse biasing the pn-junction between drift region and body region before the transistor transitions from diode state to blocking state. This is achieved by applying a negative voltage to the body region relative to the drift region, which removes charge carriers from the drift region in advance, thereby reducing the reverse recovery current and commutation losses when the transition occurs.

Inventive Principle:
Principle #10Preliminary action

2Loss of energy

If a bias voltage is applied to reverse bias the pn-junction and reduce commutation losses, then energy efficiency improves, but additional circuit complexity is introduced

Engineering Contradiction:
Improvecommutation lossesVSAvoidbias voltage application circuit
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent merges the bias voltage generation function with existing circuit elements. The body region is connected to a bias voltage source that can be integrated with the gate drive circuitry or power management circuitry already present in the system. This combining approach reduces the need for completely separate bias generation circuits, thereby limiting the increase in overall system complexity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces the commutation losses by effectively managing the charge carrier plasma and depletion region expansion, improving the efficiency of the superjunction transistor device during state transitions.

Implementation Method 1

applying a bias voltage between a bias region and at least one of a compensation region and a body region, with the bias voltage being different from zero, such that a pn-junction between the drift region and the body region and/or a pn-junction between the drift region and the compensation region is reverse biased

Methodology Applied
Scientific EffectReverse bias: Diode

Data Source

PatentEP3935737B1Transistor arrangement and electronic circuit with a transistor arrangement
Publication Date: 2024.05.29 INFINEON TECH AUSTRIA AG
  • EP3935737B1 patent drawingFigure 1
  • EP3935737B1 patent drawingFigure 2A~2B
  • EP3935737B1 patent drawingFigure 3

AI summary

A transistor arrangement and an electronic circuit with a transistor arrangement are disclosed. The transistor arrangement includes: in a semiconductor body (100), a drift region (11) of a first doping type, a compensation region (21) of a second doping type complementary to the first doping type, a body region (22) of the second doping type, and a source region (12) of the first doping type; a gate electrode (31), wherein the gate electrode (31) is coupled to a gate node (G), is dielectrically insulated from the semiconductor body (100) and is arranged in a gate trench that extends into the semiconductor body (100) and adjoins the compensation region (21); a first field electrode (551), wherein the first field electrode (551) is dielectrically insulated from the semiconductor body (100) and is arranged in a first isolation trench (51) that extends into the semiconductor body (100), wherein the first isolation trench is spaced apart from the gate trench and adjoins the compensation region (21); and a bias node (Q) different from the gate node (G) and connected to the first field electrode (551).