Superjunction Drift Layer Layout for Uniform Depletion Expansion
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Solution Overview
Problem
Existing semiconductor devices with superjunction layers face challenges in maintaining high breakdown voltage and short-circuit resistance due to uneven depletion layer expansion, which can lead to localized delays in depletion and reduced performance.
Innovation Solution
The semiconductor device incorporates a drift layer with alternating second and third semiconductor regions of specific conductivity types, arranged in elongated shapes perpendicular to each other, to ensure even depletion layer expansion and uniform breakdown voltage performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional superjunction layers with alternating n-type and p-type regions are used, then high breakdown voltage can be achieved through quick depletion, but uneven depletion layer expansion causes localized delays and reduced performance
Solution Approach 1:
The drift layer is segmented into multiple alternating second semiconductor regions (n-type) and third semiconductor regions (p-type) with different conductivity types. This segmentation creates multiple depletion paths that expand uniformly throughout the layer, preventing localized delays and ensuring even depletion expansion across the entire structure.
Solution Approach 2:
Different regions of the drift layer are assigned different conductivity types (n-type for second semiconductor regions, p-type for third semiconductor regions) to create locally optimized properties. This local quality variation ensures that depletion layers expand uniformly from multiple interfaces, resolving the uneven expansion problem while maintaining high breakdown voltage.
2Manufacturing precision
If ion implantation is used to form semiconductor regions, then precise formation of doped regions can be achieved, but resist deformation during development can occur leading to manufacturing errors
Solution Approach 1:
The patent uses opening portions with different orientations (first opening portions elongated in a first direction, second opening portions elongated in a second perpendicular direction) to form alternating semiconductor regions. This asymmetric arrangement of opening portions prevents resist deformation during development by distributing mechanical stress evenly, while still achieving precise formation of the alternating n-type and p-type semiconductor regions through selective ion implantation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for precise formation of semiconductor regions, reducing the likelihood of resist deformation during development, and achieving stable characteristics with desired breakdown voltage and short-circuit resistance.
Implementation Method 1
forming a plurality of semiconductor regions of a second conductivity type in the semiconductor layer by ion implantation of second conductivity type impurities into the semiconductor layer through the first opening portions and the second opening portions
Data Source
AI summary
A semiconductor device includes a semiconductor substrate that includes a first semiconductor layer of p-type, a drift layer disposed below the first semiconductor layer, and a second semiconductor layer of n-type disposed below the drift layer. The drift layer includes a first semiconductor region of a first conductivity type, and a plurality of second semiconductor regions of a second conductivity type and a plurality of third semiconductor regions of the second conductivity type distributed in the first semiconductor region. Each of the second semiconductor regions has a shape elongated in a first direction. Each of the third semiconductor regions has a shape elongated in a second direction that is perpendicular to the first direction. The second semiconductor regions and the third semiconductor regions are alternately arranged at intervals along the first direction, and are alternately arranged at intervals along the second direction.


