Superjunction Edge Termination Using Integrated P-Type JTE
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices with a superjunction (SJ) structure face challenges in maintaining charge balance in the edge termination region, leading to unbalanced charge distribution.
Innovation Solution
The superjunction semiconductor device incorporates a parallel pn layer with alternating regions of first and second conductivity types in both the active and termination regions. The p-type region constituting the uppermost portion of the p-type regions in the parallel pn layer serves as the junction termination extension (JTE) structure, eliminating overlap and ensuring balanced charge distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate JTE structure is provided in the termination region, then voltage withstanding capability is improved, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent merges the JTE structure with the parallel pn layer by making the p-type region of the parallel pn layer extend into the termination region. This integration eliminates the need for a separate JTE structure while maintaining voltage withstanding capability, thereby reducing device complexity and manufacturing process complexity
Solution Approach 2:
The p-type region of the parallel pn layer serves dual functions: it forms part of the active superjunction structure in the active region and simultaneously provides the JTE function in the termination region. This multi-functionality reduces the number of separate structures needed while maintaining both charge balance and voltage withstanding capabilities
2Reliability
If a separate JTE structure is provided in the termination region, then voltage withstanding capability is improved, but manufacturing process complexity and costs increase
Solution Approach 1:
The patent combines the formation of the parallel pn layer and JTE structure into a single manufacturing process. The p-type and n-type regions are alternately formed in one continuous process that extends through both the active and termination regions, eliminating the need for separate JTE formation steps and reducing manufacturing complexity
Solution Approach 2:
The JTE structure is formed simultaneously with the parallel pn layer during the same epitaxial growth process. By preparing both structures in advance during a single manufacturing sequence, the patent eliminates subsequent separate processing steps, thereby simplifying the overall manufacturing process
3Stability of the object's composition
If parallel pn layers with alternating conductivity types are provided in both active and termination regions, then charge balance is improved, but device complexity increases
Solution Approach 1:
The patent merges the charge-balancing function with the voltage-withstanding function by extending the parallel pn layer structure into the termination region. This single integrated structure simultaneously achieves charge balance through alternating p-type and n-type regions and provides voltage withstanding capability through the JTE effect, thereby reducing overall device complexity
Data Source
AI summary
A semiconductor device includes, in an active region and a termination region of a semiconductor substrate, a parallel pn layer in which regions of a first conductivity type and regions of a second conductivity type are disposed repeatedly alternating with each other. The semiconductor device further includes a third semiconductor region of the second conductivity type, configuring a voltage withstanding structure, in the termination region. Each of the regions of the second conductivity type includes multiple sub-regions stacked on one another, the multiple sub-regions including a topmost subregion that is closest to a first main surface of the semiconductor substrate. The third semiconductor region is formed at least partially by the plurality of topmost sub-regions in the termination region.