Superjunction Gate Oxide Layout for Lower Gate-Drain Capacitance
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Solution Overview
Problem
High-voltage semiconductor devices with a superjunction structure face challenges in reducing gate-drain parasitic capacitance, which affects switching speed and increases switching loss due to the full contact of the gate electrode with the gate oxide layer, leading to unnecessarily low switching speed.
Innovation Solution
A superjunction semiconductor device is designed with a gate insulating layer having an uppermost end higher than the gate oxide layer, and formed simultaneously with the field oxide layer, reducing gate-drain parasitic capacitance and increasing switching speed without requiring an additional process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate electrode is in full contact with the gate oxide layer, then the manufacturing process is simple, but the gate-drain parasitic capacitance increases and switching speed decreases
Solution Approach 1:
The gate electrode is divided into two distinct portions: a first portion that contacts the gate oxide layer and a second portion that contacts the field oxide layer. This segmentation reduces the overlapping area between the gate electrode and the drain region, thereby reducing gate-drain parasitic capacitance and improving switching speed while maintaining manufacturing simplicity.
Solution Approach 2:
The field oxide layer serves as an intermediary structure between the gate electrode and the drain region. By extending the field oxide layer to contact the second portion of the gate electrode, the patent creates an insulating barrier that reduces parasitic capacitance without requiring complex manufacturing processes.
Data Source
AI summary
Disclosed are a superjunction semiconductor device and a method of manufacturing the same. More particularly, the present disclosure relates to a superjunction semiconductor device and a method of manufacturing the same, in which the device includes a field oxide layer having an uppermost end or surface that is higher than that of a gate oxide layer, between a gate electrode and a second pillar region in a cell region. This enables a reduction in gate-drain parasitic capacitance, thereby increasing switching speed and reducing switching loss.