Superjunction Device Implant Mask Alignment
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Solution Overview
Problem
Conventional manufacturing technologies for high voltage semiconductor power devices with super-junction structures face challenges in reducing series resistance and achieving stringent charge balance requirements due to uncontrollable variations in N charge doping of epitaxial layers, especially for devices with small pitches.
Innovation Solution
A method involving the simultaneous definition of P-implant and N-implant windows using hard masks formed by oxide or photoresist layers, with repeated application of implant masks to grow multiple epitaxial layers and implant dopant regions of alternating conductivity types, allowing for precise control of critical dimensions and charge balance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional double implant processes are applied to form the super-junction, then the N charge variation can be controlled within 1% to 2%, but the charge variation increases to 10 to 20% due to critical dimension variation in controlling the alignment of dopant implantations
Solution Approach 1:
The patent combines the definition of P-implant windows and N-implant windows into a single photolithography step using one photoresist layer and one development process. This merging of two separate mask alignment operations into one simultaneous definition eliminates the cumulative alignment errors that occur when two separate masks are applied sequentially, directly resolving the charge balance precision issue caused by critical dimension variation.
Solution Approach 2:
The patent performs preliminary action by defining both P- and N-implant windows together before any doping occurs. The photoresist pattern is formed in advance to simultaneously define both implant regions, ensuring that the critical dimensions for both windows are controlled in a single process step, preventing subsequent alignment variations.
2Ease of manufacture
If multiple implant masks are applied using conventional manufacturing process, then the device structure can be formed, but the charge variation may increase to 10 to 20% due to critical dimension variation
Solution Approach 1:
The patent merges the formation of P-implant windows and N-implant windows into a single photolithography process step. Instead of applying multiple masks sequentially, both window patterns are defined simultaneously in one exposure and development cycle, maintaining process simplicity while eliminating the alignment precision degradation that would result from multiple separate masking operations.
3Reliability
If the target RdsA is reduced from 20 mohm/cm2 to 10 mohm/cm2, then the device performance is improved, but the allowable charge balance variation is reduced from 30% to 10%
Solution Approach 1:
The patent applies the merging principle to simultaneously define both P- and N-implant windows, which provides the precise charge balance control needed to meet the stringent 10% allowable variation when targeting RdsA of 10 mohm/cm2. This single-step definition ensures that both implant regions are precisely controlled without the alignment variations that would occur with separate masking processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces charge variations and improves the alignment of doped columns, enhancing the performance of super-junction devices by maintaining charge balance and reducing series resistance, thus meeting more stringent design windows for high voltage applications.
Implementation Method 1
applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer
Implementation Method 2
forming a first hard mask layer on top of the epitaxial layer
Data Source
AI summary
A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.