Super-junction MOSFET Manufacturing Method Reducing Impurity Diffusion
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Solution Overview
Problem
The manufacturing process of super-junction MOSFETs faces challenges with high manufacturing costs and low breakdown-voltage-related yield due to impurity diffusion and variations in impurity concentrations, leading to increased on-resistance and reduced breakdown voltage, particularly in the buried-trench epitaxial method.
Innovation Solution
A manufacturing method that forms MOS gate structures before the p-type/n-type column structure, reducing the number of thermal history events and minimizing impurity diffusion by depositing epitaxial layers in trenches and using high-impurity-concentration regions to enhance breakdown resistance, while maintaining a step-like impurity concentration profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If MOS gate structures are formed after the p-type/n-type column structure using conventional buried-trench epitaxial method, then the manufacturing process can be completed, but impurity diffusion occurs during thermal history events causing net doping concentration to decrease and breakdown voltage to deteriorate
Solution Approach 1:
The patent applies preliminary action by forming the MOS gate structures (including source regions and gate oxide) before creating the p-type/n-type column structure. This sequence prevents subsequent thermal history events from causing impurity diffusion in the columns, thereby maintaining precise net doping concentration control while still completing the manufacturing process.
2Reliability
If p-type and n-type impurity dopes are set higher to compensate for mutual diffusion, then on-resistance can be maintained, but variations in impurity dopes increase leading to lower breakdown-voltage-related yield
Solution Approach 1:
By forming MOS gate structures before the column structure, the patent eliminates the need to compensate for impurity diffusion. This allows impurity dopes to be set at optimal levels without excessive compensation, maintaining both on-resistance control and breakdown voltage consistency, thereby improving manufacturing precision.
3Manufacturing precision
If multi-stage epitaxial method is used to form p-type/n-type column structure, then the super-junction structure can be realized, but the manufacturing process becomes long and complex increasing manufacturing cost
Solution Approach 1:
The patent inverts the conventional manufacturing sequence by forming MOS gate structures before the p-type/n-type column structure instead of after. This inversion simplifies the overall process by eliminating the need for subsequent thermal processing steps that would cause impurity diffusion, thereby reducing manufacturing complexity while maintaining structural precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method increases the breakdown-voltage-related yield by reducing impurity dopant variations and minimizing thermal history effects, resulting in improved electrical characteristics and reduced manufacturing costs.
Implementation Method 1
An epitaxial layer to serve as a drift layer is grown on a low-resistivity semiconductor substrate
Implementation Method 2
the impurities in the p-type and n-type columns move by diffusion due to thermal history that is necessary for formation of the MOS gate structures
Implementation Method 3
Trenches are formed at prescribed intervals, so as to penetrate through the n-type epitaxial layer and reach the low-resistivity n-type semiconductor substrate, by performing etching from the wafer front side
Data Source
AI summary
A manufacturing method for a super-junction semiconductor device is disclosed. The method includes a first step of depositing, on a low-resistivity semiconductor substrate of one conductivity type, at least an epitaxial layer of the one conductivity type which is to become a drift layer; a second step of forming a base region(s) of the other conductivity type and source regions of the one conductivity type to be used for formation of MOS gate structures; a third step of forming, by anisotropic vapor-phase etching using an insulating film mask, trenches that penetrate through the base region(s) and reach the low-resistivity semiconductor substrate or its vicinity; and a fourth step of burying epitaxial layers of the other conductivity type in the respective trenches, the first to fourth steps being executed in this order.