Super-junction MOSFET with Non-uniform Pillar Charge Distribution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Super-junction MOSFETs face challenges in down-sizing while maintaining high switching speed, as it leads to electromagnetic interference (EMI), voltage overshoot, and gate voltage oscillation due to reduced parasitic capacitance, which affects reliability and stability.
Innovation Solution
A semiconductor device design with alternating P and N pillars, where the upper region is P-rich and the lower region is N-rich, with a balanced charge distribution, gradually increasing charge in the upper portions and decreasing in the lower portions, to slow down the depletion layer width increase and enhance parasitic capacitance, thereby stabilizing the drain voltage and reducing EMI and oscillation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the chip is down-sized to increase switching speed, then the capacitance between gate and drain is reduced and switching speed increases, but electromagnetic interference problems occur and reliability decreases
Solution Approach 1:
The patent applies local quality by creating non-uniform charge distribution within the drift layer. The impurity concentration is designed to vary spatially, with higher concentration near the surface and lower concentration deeper in the layer. This localized variation in electrical properties allows different regions to serve different functions: the high-concentration region near the surface increases parasitic capacitance to suppress EMI and oscillation, while the overall thin drift layer structure maintains high switching speed.
2Speed
If the chip is down-sized to increase switching speed, then the capacitance between gate and drain is reduced, but voltage overshoot and gate voltage oscillation increase
Solution Approach 1:
The patent applies parameter changes by modifying the impurity concentration parameter within the drift layer. Instead of using a uniform concentration, the concentration is varied as a function of depth from the surface. This parameter variation changes the electrical characteristics of the device, specifically increasing the parasitic capacitance between gate and drain, which in turn suppresses voltage overshoot and gate voltage oscillation during switching operations.
3Strength
If the breakdown voltage is increased in a planar MOSFET, then the drift layer is thickened, but on-resistance increases
Solution Approach 1:
The patent applies segmentation by dividing the drift layer into regions with different impurity concentrations. The drift layer is segmented such that the upper region near the surface has higher impurity concentration while the lower region has lower concentration. This segmentation allows the structure to achieve high breakdown voltage through the overall drift layer thickness while maintaining low on-resistance through the high-concentration region that reduces resistive losses.
Solution Approach 2:
The patent applies local quality by creating spatially varying impurity concentration within the drift layer. The local electrical properties are optimized for different functions: the high-concentration region near the surface reduces on-resistance and improves conductivity, while the overall drift layer structure maintains high breakdown voltage. This local optimization of material properties resolves the contradiction between low resistance and high voltage capability.
Data Source
AI summary
A semiconductor device is provided. A semiconductor device includes: a first semiconductor layer having an N-type conductivity; and a second semiconductor layer that is formed on the first semiconductor layer, wherein an active region is defined in the first semiconductor layer and the second semiconductor layer, the active region includes a plurality of first P pillars and a plurality of first N pillars alternately arranged along a first direction, in the active region, an upper pillar region including an upper region of the plurality of first P pillars and an upper region of the plurality of first N pillars, a lower pillar region including a lower region of the plurality of first P pillars and a lower region of the plurality of first N pillars, and a middle pillar region formed between the upper pillar region and the lower pillar region are defined, the entire charge amount of the upper pillar region is greater than the entire charge amount of the lower pillar region, and a P-type charge amount is greater than an N-type charge amount in the upper pillar region, while the N-type charge amount is greater than the P-charge amount in the lower pillar region.