Super Junction MOSFET Pillar Layout for Lower Switching EMI
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Solution Overview
Problem
Traditional super junction MOSFET devices have a fixed width for N-type pillars, leading to uniform depletion rates and fast switching speeds, which result in susceptibility to electromagnetic interference (EMI).
Innovation Solution
The super junction MOSFET device incorporates a super junction structure with second conductive type pillars that are partially or wholly displaced, providing multiple transverse dimensions for first conductive type pillars. This variation in pillar spacing results in different lateral depletion rates, slowing down the depletion process and reducing capacitance changes during switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the N-type pillar width is fixed in traditional super junction MOSFET devices, then the depletion rate of the P-type pillar to the N-type pillar is uniform and fast, resulting in fast switching speed, but this causes electromagnetic interference (EMI) problems
Solution Approach 1:
The patent applies local quality by creating different N-type pillar widths in different regions of the device. Specifically, the N-type pillar width varies in the transverse direction, with some regions having wider pillars and others having narrower pillars. This local variation in geometry creates different depletion rates in different regions, resulting in a more gradual overall capacitance change during switching, thereby reducing EMI while maintaining fast switching performance.
Solution Approach 2:
The patent introduces asymmetry by deliberately making the N-type pillar widths non-uniform across the device structure. Instead of symmetric, identical pillars throughout, the design employs asymmetric pillar dimensions where adjacent N-type pillars have different widths. This asymmetric configuration creates a distribution of depletion rates that smooths the switching transition and reduces electromagnetic interference.
2Reliability
If the N-type pillar width is increased to reduce on-resistance, then the on-resistance decreases, but the depletion rate becomes even faster, worsening the EMI problem
Solution Approach 1:
The patent resolves this contradiction by applying local quality through spatially varying N-type pillar widths. In regions where lower on-resistance is critical, wider N-type pillars are used to reduce resistance. In other regions, narrower pillars are employed to control the depletion rate and mitigate EMI. This local optimization allows the device to achieve low overall on-resistance while preventing excessively fast depletion rates that would cause EMI.
Solution Approach 2:
The patent employs parameter changes by varying the geometric parameters of the N-type pillars (specifically width) across different regions. This parameter variation allows optimization of both on-resistance and EMI characteristics simultaneously - wider pillars reduce resistance while narrower pillars control depletion speed, achieving a balance between these two competing requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The modified super junction MOSFET device effectively mitigates electromagnetic interference by reducing the rapid voltage changes during switching, thereby enhancing the device's performance and reliability.
Implementation Method 1
the P-type pillar and N-type pillar deplete each other, so the drift region is similar to the intrinsic region, and the electric field in the drift region is optimized from the triangular distribution of the conventional MOSFET device to an approximate trapezoidal distribution
Implementation Method 2
one or more of the plurality of second conductive type pillars are partially and/or wholly displaced to provide two or more different transverse dimensions for the plurality of first conductive type pillars; The different spacings between the second conductive type pillars result in different lateral depletion rates
Implementation Method 3
the depletion rate of the P-type pillar to the N-type pillar is very fast, making the junction capacitance of the super junction MOSFET device much smaller than that of the planar MOSFET device
Data Source
AI summary
A super junction MOSFET device, including: a substrate having a first conductive type; a buffer layer having the first conductive type and disposed on the substrate; a super junction structure disposed on the buffer layer and including multiple first conductive type pillars and multiple second conductive type pillars alternately arranged in a transverse direction, several second conductive type pillars being partially and/or wholly displaced to provide two or more different transverse dimensions for the first conductive type pillars; a body region having the second conductive type and disposed on a top of the second conductive type pillar; a source structure located within the body region and including a source region having the first conductive type and an ohmic contact region having the second conductive type which contacts with the source region; and a gate structure in contact with the first conductive type pillar and the source structure.