Superjunction MOSFET Reverse Biasing for Lower Reverse Recovery Loss
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Solution Overview
Problem
Superjunction transistor devices experience significant losses during the transition from a diode state to a blocking state due to the reverse recovery current, which affects both the device itself and connected components.
Innovation Solution
Applying a bias voltage between the bias region and at least one of the compensation region and the body region, with the bias voltage being different from zero and reverse biasing the pn-junctions, helps to reduce these losses by facilitating the removal of charge carriers and charging of junction capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the MOSFET operates in diode state with charge carrier plasma in the drift region, then the device can conduct current in the reverse direction, but significant commutation losses occur when transitioning to blocking state due to reverse recovery current
Solution Approach 1:
The patent applies a reverse bias voltage to the body diode before the transition from diode state to blocking state, which preliminarily removes charge carriers from the drift region and reduces the reverse recovery current that would otherwise cause commutation losses. This preliminary action prepares the device for efficient switching by reducing the plasma concentration in advance.
Solution Approach 2:
The patent changes the voltage parameter applied to the body diode from forward bias (during diode conduction) to reverse bias (during transition to blocking state). This parameter change controls the depletion region width and charge carrier concentration in the drift region, enabling reduction of commutation losses while maintaining reverse conduction capability.
2Loss of energy
If a reverse bias voltage is applied to remove charge carriers and form depletion region, then commutation losses are reduced, but additional control circuitry and voltage application mechanisms are required
Solution Approach 1:
The gate electrode structure serves multiple functions: it controls the MOSFET channel conduction and simultaneously controls the body diode bias state. By utilizing the existing gate electrode and its connection to the body region, the patent achieves reverse bias application without requiring separate dedicated control structures, thereby reducing additional complexity.
Solution Approach 2:
The patent utilizes the intrinsic relationship between the gate electrode and body diode to achieve automatic reverse biasing during the transition to blocking state. The control mechanism leverages the device's own structure and operating states to accomplish the charge carrier removal function without requiring external complex control circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the commutation losses associated with transitioning from the diode state to the blocking state by efficiently managing the charge carrier plasma and junction capacitance, improving the overall efficiency of the superjunction transistor device.
Implementation Method 1
the bias voltage being different from zero and reverse biasing the pn-junctions
Implementation Method 2
as the load path voltage increases a depletion region (space charge regions) is formed in the drift region
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
A method and a transistor arrangement are disclosed. The method includes: applying a bias voltage (VDEP) different from zero between a drift region (11) and at least one of a compensation region (21) and a body region (22) of at least one transistor cell (10) of a transistor device when the transistor device is in a diode state, wherein the compensation region (21) has a doping type complementary to a doping type of the drift region (11), wherein the compensation region (21) adjoins the drift region (11), wherein a polarity of the bias voltage (VDEP) is such that a pn-junction between the drift region (11) and the at least one of the compensation region (21) and the body region (22) is reverse biased, wherein applying the bias voltage (VDEP) comprises applying the bias voltage (VDEP) between a bias region (4) that is coupled to the drift region (11) and the at least one of the compensation region (21) and the body region (22), and wherein the bias region (4) is spaced apart from a body region (22) and a source region (12) of the at least one transistor cell.