Superjunction Pillar Layout for Breakdown-Stable Semiconductor Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Super-junction semiconductor devices face charge imbalance issues, leading to poor breakdown characteristics and potential damage due to pillar structures, necessitating a design that balances charge changes effectively.
Innovation Solution
A semiconductor device structure with specific layer configurations, including active, frame, and termination regions with varying P-type and N-type pillars and impurity concentrations, is implemented to balance charge amounts and adjust depletion region expansion uniformly, preventing damage from high electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If pillar structures are alternately disposed to reduce on-resistance, then on-resistance decreases and switching speed improves, but charge imbalance occurs leading to poor breakdown characteristics
Solution Approach 1:
The drift layer is segmented into multiple regions with alternating P-type and N-type pillars arranged in a columnar structure. This segmentation allows for controlled charge distribution while maintaining low on-resistance. The pillars are divided into first pillars extending from the gate electrode and second pillars extending from the opposite surface, creating a balanced charge structure that prevents breakdown.
Solution Approach 2:
Different regions of the semiconductor device are given different local properties. The first pillars and second pillars have different conductivity types and extension directions, creating local variations in charge distribution. This local quality differentiation ensures that charge imbalance is prevented at critical interfaces while maintaining overall device performance.
2Reliability
If breakdown voltage is increased by thickening the drift layer, then breakdown voltage increases, but on-resistance increases
Solution Approach 1:
The device structure employs asymmetric pillar arrangement where first pillars extend from the gate electrode side and second pillars extend from the opposite surface. This asymmetric configuration allows the drift layer to be sufficiently thick for high breakdown voltage while the alternating pillar structure maintains low on-resistance by providing multiple charge compensation paths.
Solution Approach 2:
The charge balance is achieved not only in the vertical dimension through pillar extension but also in the horizontal dimension through alternating P-type and N-type pillar arrangement. This multi-dimensional approach allows thick drift layer design for high breakdown voltage without sacrificing on-resistance performance.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes: a first semiconductor layer having an N-type of conductivity; and a second semiconductor layer that is formed on the first semiconductor layer, and including an active region, a frame region, and a termination region, wherein the active region includes a plurality of first P-pillars and first N-pillars formed between the plurality of first P-pillars, the frame region includes an upper frame region formed to extend in a first direction while having a P-type of conductivity, and a lower frame region that is formed below the upper frame region and including a plurality of second P-pillars and second N-pillars formed between the plurality of second P-pillars, and the termination region includes an upper termination region that extends in the first direction while having the P-type of conductivity, a middle termination region having the N-type of conductivity and formed below the upper termination region, and a lower termination region formed below the middle termination region and including a plurality of third P-pillars and third N-pillars formed between the plurality of third P-pillars.