Super Junction Power MOSFET Trench Layout for Stable Gate-Drain Capacitance
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Solution Overview
Problem
Super junction semiconductor power devices experience sudden changes in gate-drain capacitance during switching, leading to electrical property changes and increased switching losses.
Innovation Solution
A super junction semiconductor power device design with multiple p-type columns and gate trenches of varying spacings, along with a double-trench gate structure, adjusts the gate-drain capacitance variation curve, reducing sudden changes and oscillations by distributing the depletion across multiple voltage points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a super junction semiconductor power device uses uniform trench spacing, then the device structure is simple and easy to manufacture, but the gate-drain capacitance changes suddenly during switching
Solution Approach 1:
The patent applies local quality by making the trench spacing non-uniform, with different spacing values in different regions. Specifically, the spacing between adjacent trenches varies, creating local differences in the electric field distribution and capacitance characteristics. This local variation smooths the gate-drain capacitance change during switching while maintaining overall device functionality.
2Productivity
If the device operates with fast switching characteristics, then power conversion efficiency is improved, but gate-drain capacitance fluctuation increases
Solution Approach 1:
The patent changes the geometric parameter of trench spacing to optimize the capacitance characteristics. By adjusting the spacing between trenches to have at least two different values, the device modifies the electric field distribution and capacitance variation profile, enabling fast switching while reducing capacitance fluctuations and improving electrical stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces the sudden change speed of gate-drain capacitance and oscillations, enhancing switching characteristics and power conversion efficiency.
Implementation Method 1
When a super junction semiconductor power device is turned on and off, gate-drain capacitance (Cgd) may change suddenly. As a result, the electrical property of the super junction semiconductor power device also changes suddenly.
Data Source
AI summary
A super junction semiconductor power device includes an n-type drain region, an n-type drift region, multiple p-type columns, and two gate trenches. The n-type drift region is located on the n-type drain region. The multiple p-type columns have the same width. The spacing between two adjacent p-type columns is the same. A first p-type body region is disposed on the top of each p-type column. The first p-type body region is provided with a first n-type source region. Two gate trenches are between two adjacent first p-type body regions. The spacing between the two gate trenches has at least two different spacing values. The widths of the two gate trenches between the two adjacent first p-type body regions are the same. Each gate trench is provided with a gate dielectric layer and a gate.