Superjunction Trench Transistor Layout for Gate-Drain Capacitance Tuning
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Solution Overview
Problem
Conventional superjunction transistor devices face challenges in improving short-circuit robustness and adjusting gate-drain capacitance, which affects switching speed and efficiency.
Innovation Solution
The design incorporates a compensation region that adjoins both dielectric layers, forming a pn-junction with the drift region, and allows for varying connections of trench electrodes to gate or source nodes, enabling adjustment of gate-drain capacitance through different transistor cell configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional superjunction transistor devices are used, then the device structure is simple, but short-circuit robustness is insufficient
Solution Approach 1:
The transistor device is divided into multiple transistor cells, each containing separate source regions and body regions arranged in mesa regions between trench electrodes. This segmentation allows independent control and optimization of each cell's short-circuit behavior, improving overall robustness while maintaining a systematic structure
Solution Approach 2:
Dielectric layers are introduced as intermediary elements between the trench electrodes and the semiconductor body, and between different regions. These dielectric layers provide electrical isolation and control, enabling improved short-circuit robustness through controlled charge distribution without requiring complete structural redesign
2Speed
If gate-drain capacitance is reduced to improve switching speed, then switching performance improves, but control flexibility is limited
Solution Approach 1:
The transistor device enables dynamic adjustment of gate-drain capacitance through different connection configurations of the trench electrodes. The first and second trench electrodes can be connected to different nodes (gate node or source node), allowing the device to adapt its electrical characteristics for optimal switching performance under different operating conditions
Solution Approach 2:
The invention provides flexibility in adjusting gate-drain capacitance by varying the connection configuration of trench electrodes to different potential nodes. This parameter adjustment capability allows optimization of switching speed while maintaining control flexibility across different application scenarios
3Ease of operation
If trench electrodes are connected to gate node only, then gate control is simplified, but capacitance adjustment flexibility is reduced
Solution Approach 1:
The trench electrodes are designed with multi-functionality, capable of being connected to different nodes (gate node or source node) depending on the desired operating mode. This universal connection capability allows the same physical structure to serve multiple functions: simplified gate control when connected to gate node, or capacitance optimization when connected to source node
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances short-circuit robustness and provides flexibility in adjusting switching speed by optimizing gate-drain capacitance, improving overall transistor device performance.
Implementation Method 1
a first trench electrode insulated from the semiconductor body by a first dielectric layer, a second trench electrode insulated from the semiconductor body by a second dielectric layer
Implementation Method 2
a compensation region. The compensation region adjoins the body region, the first dielectric layer and the second dielectric layer, and forms a pn-junction with the drift region
Data Source
AI summary
A transistor device is disclosed. The transistor device includes: a semiconductor body (100); a drift region (11) in the semiconductor body (100); a plurality of transistor cells (10); and a gate node (G) and a source node (S), wherein each of the plurality of transistor cells (10) includes: a first trench electrode (21) insulated from the semiconductor body (100) by a first dielectric layer (22); a second trench electrode (23) insulated from the semiconductor body (100) by a second dielectric layer (24); a source region (13) and a body region (14) in a first mesa region (111) between the first trench electrode (21) and the second trench electrode (23); and a compensation region (12), wherein the compensation region (12) adjoins the body region (14), the first dielectric (22), the second dielectric (24), and forms a pn-junction with the drift region (11), and wherein from the first trench electrode (21) and the second trench electrode (23) at least the first trench electrode (21) is connected to the gate node (G).