Superjunction Trench Transistor Layout for Robust Fast Switching
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Solution Overview
Problem
Conventional superjunction transistor devices face limitations in design flexibility and short-circuit robustness, particularly in the integration of compensation regions with dielectric layers, which affects switching speed and reliability.
Innovation Solution
The design incorporates a superjunction transistor device with a compensation region that adjoins both dielectric layers, forming pn-junctions with the drift region, and features a gate node connection to trench electrodes, enhancing the conducting channel along the dielectric layers and allowing for adjustable gate-drain capacitance by varying the ratio of transistor cell types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the compensation region is integrated with dielectric layers in conventional superjunction transistor devices, then the device structure is compact, but the short-circuit robustness and switching speed are limited
Solution Approach 1:
The device is divided into multiple transistor cells (first type and second type) with different configurations. The first transistor cells have compensation regions adjoining both dielectric layers, while the second transistor cells have compensation regions adjoining only the first dielectric layer. This segmentation allows independent optimization of different cell types for different functions, improving overall short-circuit robustness while maintaining switching speed through the mixed configuration.
Solution Approach 2:
Different regions of the device are given different properties: the first transistor cells with dual-dielectric compensation regions provide enhanced short-circuit robustness, while the second transistor cells with single-dielectric compensation regions maintain faster switching characteristics. The gate node connections are also locally optimized, with some trench electrodes connected to the gate node and others not, creating local variations in electric field distribution that improve both robustness and speed.
2Speed
If the gate-drain capacitance is reduced to improve switching speed, then the switching behavior improves, but the design flexibility is constrained
Solution Approach 1:
The device provides dynamic adjustability of gate-drain capacitance through the configurable ratio of first to second transistor cells. By varying this ratio, the overall gate-drain capacitance can be tuned to optimize switching speed for different applications. The connection configuration of trench electrodes to the gate node is also dynamic, allowing different electric field distributions and capacitance values to be achieved based on operational requirements.
Solution Approach 2:
The invention changes the structural parameters of the transistor cells to achieve different gate-drain capacitance values. The first transistor cells with compensation regions adjoining both dielectric layers provide different capacitance characteristics compared to the second transistor cells with compensation regions adjoining only the first dielectric layer. By adjusting the proportion of each cell type and their respective dimensions, the gate-drain capacitance can be optimized for various switching speed requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the short-circuit robustness and switching behavior of the transistor device, offering greater design flexibility and potentially faster switching speeds by optimizing the gate-drain capacitance.
Implementation Method 1
a first trench electrode insulated from the semiconductor body by a first dielectric layer, a second trench electrode insulated from the semiconductor body by a second dielectric layer
Implementation Method 2
The compensation region adjoins the body region, the first dielectric layer and the second dielectric layer, and forms a pn-junction with the drift region
Implementation Method 3
a control structure with one or more gate electrodes. The control structure is configured to control an operating state of the transistor device
Data Source
Figure 1~2
Figure 3
Figure 4A
AI summary
A transistor device is disclosed. The transistor device includes: a semiconductor body (100); a drift region (11) in the semiconductor body (100); a plurality of transistor cells (10); and a gate node (G) and a source node (S), wherein each of the plurality of transistor cells (10) includes: a first trench electrode (21) insulated from the semiconductor body (100) by a first dielectric layer (22); a second trench electrode (23) insulated from the semiconductor body (100) by a second dielectric layer (24); a source region (13) and a body region (14) in a first mesa region (111) between the first trench electrode (21) and the second trench electrode (23); and a compensation region (12), wherein the compensation region (12) adjoins the body region (14), the first dielectric (22), the second dielectric (24), and forms a pn-junction with the drift region (11), and wherein from the first trench electrode (21) and the second trench electrode (23) at least the first trench electrode (21) is connected to the gate node (G).