Superlattice Buffer Structure for GaN Transistors

The patent introduces AlN insertion layers as intermediary elements between the silicon substrate and the GaN channel layer. These AlN layers act as stress management intermediaries that prevent tensile stress propagation through the epitaxial stack, thereby preventing wafer cracks while maintaining high resistivity buffer layers for device performance.

The patent segments the continuous buffer layer structure into discrete sections by inserting AlN layers at specific positions. This segmentation divides the stress distribution and prevents continuous tensile stress accumulation, allowing the structure to maintain both high resistivity regions and mechanical integrity.

AlN insertion layers serve as stress-blocking intermediaries that enable increased buffer layer thickness without proportional increase in tensile stress. The AlN layers interrupt stress propagation, allowing thicker buffer layers to be grown while maintaining wafer integrity and preventing cracks.

The patent changes the material composition parameter by introducing AlN layers with different mechanical properties than GaN. This parameter change in material composition allows the structure to accommodate greater total thickness while managing stress through the contrasting mechanical properties of the alternating layers.

The AlN insertion layers act as intermediaries that block tensile stress propagation from doped buffer layers. This allows dopants to be added to achieve high resistivity and improved soft breakdown voltage while the AlN layers prevent the associated tensile stress from causing wafer cracks.

The patent segments the doped buffer layer structure with undoped AlN insertion layers. This segmentation isolates the stressed doped regions from each other, preventing cumulative tensile stress while maintaining the high resistivity benefits of dopant addition in each segment.