Impurity and Point Defect Blocking Superlattice for Semiconductor Integration

Solution Overview

Problem

Current semiconductor devices face limitations in enhancing charge carrier mobility and reducing defects, particularly in heteroepitaxial growth, which affects device performance and integration of silicon alloys and compound semiconductors on patterned silicon substrates.

Innovation Solution

Incorporating an impurity and point defect blocking superlattice layer, composed of stacked semiconductor and non-semiconductor monolayers, between the substrate and active layer, to reduce effective mass of charge carriers and prevent dopant diffusion, thereby enhancing mobility and reducing defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If heteroepitaxial growth is used to integrate silicon alloys and compound semiconductors on patterned silicon substrates, then device integration is achieved, but defects and impurities increase

Engineering Contradiction:

Improvedevice integrationVSAvoiddefect reduction

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces an impurity and point defect blocking superlattice layer as an intermediary between the substrate and active layer. This superlattice acts as a barrier that prevents dopant diffusion and blocks point defects while maintaining the heteroepitaxial growth process, thus resolving the contradiction between achieving device integration and reducing defects

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If conventional semiconductor structures are used, then manufacturing is simple, but charge carrier mobility is limited

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidcharge carrier mobility

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent employs a composite superlattice structure consisting of alternating semiconductor and non-semiconductor monolayers. This composite material approach enhances charge carrier mobility by reducing effective mass and minimizing alloy scattering, while still being compatible with conventional manufacturing processes through epitaxial growth

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The superlattice structure achieves higher charge carrier mobility and reduces defects, providing a compliant interface for high-K dielectrics and improving device performance by lowering conductivity effective mass and acting as a barrier to dopant diffusion.

Implementation Method 1

The superlattice structure achieves higher charge carrier mobility and reduces defects, providing a compliant interface for high-K dielectrics and improving device performance by lowering conductivity effective mass

Methodology Applied

Scientific EffectBand structure engineering:

Implementation Method 2

Incorporating an impurity and point defect blocking superlattice layer, composed of stacked semiconductor and non-semiconductor monolayers, between the substrate and active layer, to reduce effective mass of charge carriers and prevent dopant diffusion

Methodology Applied

Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS10468245B2Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice

Publication Date: 2019.11.05 ATOMERA INC

AI summary

A semiconductor device may include a substrate including a first Group IV semiconductor having a recess therein, an active layer comprising a Group III-V semiconductor within the recess, and a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The semiconductor device may further include an impurity and point defect blocking superlattice layer adjacent the buffer layer.