Superlattice Structures with Reduced Defect Densities
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Solution Overview
Problem
Current semiconductor technologies face limitations in enhancing charge carrier mobility and reducing defect densities in advanced semiconductor processing, despite existing approaches such as strained material layers and superlattices.
Innovation Solution
A method for forming a superlattice on a substrate with stacked groups of layers, including base semiconductor monolayers and non-semiconductor monolayers constrained within the crystal lattice, using thermal anneal and etching processes to achieve reduced defect densities and enhanced mobility, with specific configurations like Si/O superlattices providing lower conductivity effective masses for charge carriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If strained material layers are used to enhance charge carrier mobility, then mobility is improved, but defect densities increase
Solution Approach 1:
The patent divides the semiconductor layer into multiple thin monolayers stacked in sequence, with non-semiconductor monolayers interspersed between semiconductor monolayers. This segmentation approach allows the structure to achieve strain-induced mobility enhancement while the fine-layered configuration prevents defect accumulation that would occur in thicker strained layers
Solution Approach 2:
The patent creates a composite superlattice structure combining semiconductor monolayers (such as silicon) with non-semiconductor monolayers (such as oxygen, carbon, or nitrogen). This composite approach enables the semiconductor layers to be strained for improved carrier mobility while the non-semiconductor layers act as buffers to reduce defect propagation
2Speed
If superlattice structures are formed to reduce alloy scattering, then mobility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the superlattice into atomic-scale monolayers that can be deposited using standard epitaxial techniques. By breaking down the complex superlattice structure into repeating units of single monolayers, the manufacturing process becomes more manageable and compatible with existing semiconductor fabrication equipment
Solution Approach 2:
The patent controls the thickness and composition parameters of each monolayer to optimize mobility while simplifying manufacturing. By precisely controlling the atomic-layer thickness and material composition during deposition, the patent achieves the desired mobility enhancement through standard process parameters rather than complex post-processing
3Reliability
If thin semiconductor layers are deposited to reduce defects, then defect density is reduced, but charge carrier mobility is limited
Solution Approach 1:
The patent incorporates non-semiconductor monolayers (such as oxygen, carbon, or nitrogen) between semiconductor monolayers to create a composite superlattice. This composite structure provides defect reduction benefits from the thin-layer configuration while the alternating layers induce strain that enhances charge carrier mobility in the semiconductor regions
Solution Approach 2:
The patent utilizes differential thermal expansion or lattice mismatch between alternating semiconductor and non-semiconductor monolayers to induce strain in the semiconductor layers. This strain, generated through the composite structure's inherent lattice differences, enhances carrier mobility without requiring the semiconductor layers to be thick
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in semiconductor devices with improved charge carrier mobility, reduced defect densities, and enhanced conductive properties, suitable for various applications including opto-electronic devices, while also acting as a barrier to dopant diffusion and scattering effects.
Implementation Method 1
at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions
Implementation Method 2
using thermal anneal and etching processes to achieve reduced defect densities
Implementation Method 3
using thermal anneal and etching processes to achieve reduced defect densities
Implementation Method 4
while also acting as a barrier to dopant diffusion and scattering effects
Data Source
AI summary
A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.