Superlattice Depletion Layer Stack for Carrier Mobility
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Solution Overview
Problem
Current semiconductor devices face limitations in enhancing charge carrier mobility and integrating advanced materials effectively, despite existing advancements in strained layers and superlattice structures.
Innovation Solution
The development of a semiconductor device with an alternating stack of superlattice and bulk semiconductor layers, where each superlattice layer includes stacked base semiconductor monolayers with a non-semiconductor monolayer constrained within the crystal lattice, forming spaced apart source and drain regions and a gate structure, along with shallow trench isolation regions, to reduce effective mass and enhance mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If strained material layers are used to enhance carrier mobility, then device speed and power performance are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The device structure is segmented into alternating superlattice and bulk semiconductor layers, with each superlattice layer containing multiple thin monolayers (less than eight monolayers thick) of different materials. This segmentation allows the complex strained material structure to be divided into manageable repeating units, reducing manufacturing complexity while maintaining the mobility enhancement benefits.
Solution Approach 2:
The patent employs composite material structures combining superlattice layers (with alternating semiconductor and non-semiconductor monolayers) and bulk semiconductor layers. This composite approach integrates the mobility-enhancing strained regions with simpler bulk regions, balancing performance improvement with manufacturing feasibility.
2Speed
If superlattice structures with multiple thin layers are implemented, then charge carrier mobility is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies precise parameter ranges to manage manufacturing precision: superlattice layers contain less than eight monolayers of alternating materials, with each monolayer being atomically thin. The bulk semiconductor layers have controlled thicknesses (e.g., 5-50 nm) to maintain precision while simplifying fabrication compared to entirely ultra-thin structures.
Solution Approach 2:
By segmenting the structure into repeating superlattice units separated by thicker bulk layers, the patent reduces the cumulative precision requirements. Each superlattice unit can be grown independently with standard precision, and the bulk layers provide tolerance buffers, making manufacturing more feasible than a continuous ultra-thin superlattice.
3Reliability
If advanced material integration is pursued to improve energy band structures, then conductive properties are enhanced, but ease of manufacture decreases
Solution Approach 1:
The patent uses composite material structures combining superlattice layers (for enhanced conductive properties through band structure engineering) with bulk semiconductor layers (for manufacturing ease). This composite approach allows advanced materials to be integrated in controlled regions while maintaining compatibility with existing manufacturing processes in bulk regions.
Solution Approach 2:
The alternating superlattice-bulk structure serves multiple functions: the superlattice regions provide enhanced conductive properties and band structure control, while the bulk regions provide mechanical support and manufacturing simplicity. This multi-functionality allows a single structure to address both performance enhancement and ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher charge carrier mobility, reduced scattering effects, and the ability to integrate materials with improved energy band structures, providing enhanced conductive properties and potential for piezoelectric, pyroelectric, and ferroelectric applications.
Implementation Method 1
each superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions
Implementation Method 2
The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices
Implementation Method 3
a Si—Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice
Data Source
AI summary
A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.