Superlattice DRAM RCAT Transistors for Mobility and Leakage
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Solution Overview
Problem
Current semiconductor devices, particularly in dynamic random access memory (DRAM) cells, face challenges with carrier mobility and gate leakage, which hinder performance improvements as technology generations advance.
Innovation Solution
The development of superlattice structures with stacked groups of semiconductor and non-semiconductor monolayers, where the non-semiconductor monolayers are constrained within the crystal lattice of adjacent semiconductor portions, reduces the effective mass of charge carriers, enhancing mobility and acting as a barrier to dopant diffusion, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor structures are used in DRAM cells, then manufacturing processes are simpler, but carrier mobility is insufficient and gate leakage increases
Solution Approach 1:
The patent employs composite superlattice structures comprising alternating layers of semiconductor materials (e.g., SiGe, SiC) and non-semiconductor materials (e.g., SiO2, Si3N4). This composite approach enables simultaneous achievement of high carrier mobility through strained semiconductor layers and effective gate leakage blocking through insulating layers, resolving the technical contradiction between device performance and structural complexity.
Solution Approach 2:
The superlattice structure implements local quality by assigning different functional properties to different layers: semiconductor layers provide high carrier mobility and strain effects, while non-semiconductor layers provide gate leakage barriers and dopant diffusion barriers. This localized functional differentiation resolves the contradiction by optimizing each layer for its specific purpose rather than using a uniform structure.
2Productivity
If technology generations advance, then device density increases, but carrier mobility degradation and gate leakage worsen
Solution Approach 1:
The patent utilizes parameter changes by varying the thickness, composition, and strain state of individual layers within the superlattice structure. By adjusting these parameters, the device can maintain high carrier mobility even as overall device density increases across technology generations, counteracting the typical mobility degradation associated with scaling.
3Ease of manufacture
If conventional materials are used, then manufacturing is easier, but dopant diffusion control is insufficient
Solution Approach 1:
The non-semiconductor layers (e.g., SiO2, Si3N4) within the superlattice structure serve as intermediary barrier layers that prevent dopant diffusion between adjacent semiconductor regions. These intermediary layers enable precise dopant profile control while using materials that are compatible with existing semiconductor manufacturing processes, thus resolving the contradiction between ease of manufacture and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The superlattice structure increases charge carrier mobility and reduces gate leakage, leading to enhanced DRAM performance with improved drivability and retention times, while also providing a direct energy bandgap beneficial for opto-electronic devices.
Implementation Method 1
reduces the effective mass of charge carriers, enhancing mobility
Implementation Method 2
acting as a barrier to dopant diffusion
Data Source
AI summary
A method for making a semiconductor device may include forming at least one memory array including a plurality of recessed channel array transistors (RCATs) on a substrate, and forming periphery circuitry adjacent the at least one memory array and comprising a plurality of complementary metal oxide (CMOS) transistors on the substrate. Each of the CMOS transistors may include spaced-apart source and drain regions in the substrate and defining a channel region therebetween, and a first superlattice extending between the source and drain regions in the channel region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may be over the first superlattice and between the source and drain regions.