Superlattice DRAM Sense Amplifier for Lower Standby Power
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Solution Overview
Problem
Current DRAM devices face challenges in minimizing power consumption during standby mode and optimizing latency, particularly due to leakage in the periphery and the need for frequent data refresh.
Innovation Solution
The proposed DRAM device incorporates a superlattice structure in its transistors, including a precharge circuit, sense amplifier, and refresh circuit, to manage reference voltages and enhance charge carrier mobility, thereby reducing power consumption and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional transistors are used in DRAM devices, then the device complexity is lower and manufacturing is easier, but charge carrier mobility is insufficient leading to higher power consumption and latency
Solution Approach 1:
The patent applies composite materials by integrating a superlattice structure (alternating layers of different semiconductor materials) into the transistor channel. This composite structure combines materials with different bandgaps and carrier mobilities to create a channel that achieves higher overall charge carrier mobility than conventional single-material transistors, thereby reducing power consumption while accepting increased structural complexity
Solution Approach 2:
The patent changes the physical parameters of the transistor channel by replacing the conventional uniform semiconductor material with a superlattice structure having varying material composition and thickness at the nanometer scale. This parameter change at the material level enables enhanced charge carrier mobility through quantum confinement effects and band structure engineering, directly addressing the power consumption issue
2Loss of time
If conventional transistors are used in DRAM devices, then the manufacturing process is simpler, but latency performance is degraded due to insufficient charge carrier mobility
Solution Approach 1:
The superlattice channel constructed from composite semiconductor materials provides enhanced charge carrier mobility through the quantum mechanical effects arising from the layered structure. This composite material approach reduces the time for charge carriers to traverse the channel, thereby reducing latency while introducing manufacturing complexity
Solution Approach 2:
The patent introduces a new dimension of control by structuring the channel in alternating nanometer-thin layers (superlattice) rather than as a uniform bulk material. This dimensional structuring at the nanoscale creates quantum confinement effects that enhance carrier mobility and reduce transit time, addressing latency while increasing structural complexity
3Use of energy by moving object
If reference voltages are not properly managed in standby mode, then power consumption increases due to leakage, but voltage stability may be compromised
Solution Approach 1:
The patent implements preliminary action by pre-charging the bit lines to reference voltages before the actual read operation and by selectively maintaining these reference voltages during standby mode. This advance preparation and maintenance of voltage levels prevents leakage-induced voltage drift while enabling rapid data access, thereby managing power consumption without compromising voltage stability
Solution Approach 2:
The patent employs feedback mechanisms through the sense amplifier that continuously monitors and compares the voltage on bit lines against reference voltages. This feedback system detects voltage deviations caused by leakage and corrects them by amplifying the differential signal, thereby maintaining voltage stability while managing power consumption during standby and active modes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of superlattice transistors in the DRAM device leads to improved charge carrier mobility, reduced power consumption during standby mode, and enhanced latency performance, extending battery life in portable devices.
Implementation Method 1
The superlattice channel may include a plurality of stacked groups of layers, with group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions
Data Source
AI summary
A dynamic random access memory (DRAM) device may include an array of DRAM cells, with each DRAM cell configured to store a high logic voltage and a low logic voltage. The DRAM device may further include a precharge circuit configured to selectively provide a first reference voltage and a second reference voltage to a first line and a second line, respectively, and a sense amplifier comprising a cross-coupled transistor sensing circuit coupled between the first line and second line. The sense amplifier may include at least one transistor including a superlattice channel. The DRAM device may further include a refresh circuit configured to selectively couple a third reference voltage to a corresponding DRAM cell via the first line and based upon a voltage difference between the first line and the second line, with the third reference voltage being greater than the high logic voltage of the DRAM cell.