HfO2-ZrO2 Superlattice Gate Stack Without SiO2 Scavenging
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Solution Overview
Problem
Conventional high-κ dielectric gate stacks in advanced transistors face challenges in achieving increased gate capacitance while minimizing leakage current and mobility degradation, as the thinner SiO2 layers required for scaling lead to undesirable electrical properties.
Innovation Solution
The implementation of HfO2—ZrO2 superlattice heterostructures with mixed ferroelectric-antiferroelectric order, stabilized using atomic layer deposition, which achieves a lower effective oxide thickness and higher capacitance without the need for scavenging the interfacial SiO2 layer, thereby reducing leakage current and maintaining mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If the interfacial SiO2 layer is thinned to achieve lower effective oxide thickness and higher capacitance, then gate capacitance is improved, but leakage current increases and mobility degrades
Solution Approach 1:
The gate stack is segmented into multiple functional layers: a thin interfacial SiO2 layer (8-10 nm) that maintains low leakage, a high-κ HfO2 layer (2-3 nm) that provides high capacitance, and an optional scavenged SiO2 layer that is selectively removed to further reduce EOT. This segmentation allows each layer to optimize its function without compromising the others.
Solution Approach 2:
The gate stack employs a composite structure combining SiO2 and HfO2 materials with different dielectric properties. The SiO2 provides low leakage current characteristics while the HfO2 provides high dielectric constant, creating a composite system that achieves both low EOT and low leakage current simultaneously.
2Stress or pressure
If the interfacial SiO2 layer is thinned to achieve lower effective oxide thickness, then capacitance is improved, but mobility degrades
Solution Approach 1:
The gate stack is segmented into multiple functional layers: a thin interfacial SiO2 layer (8-10 nm) that maintains low leakage, a high-κ HfO2 layer (2-3 nm) that provides high capacitance, and an optional scavenged SiO2 layer that is selectively removed to further reduce EOT. This segmentation allows each layer to optimize its function without compromising the others.
Solution Approach 2:
The dielectric constant (κ) parameter is changed by introducing HfO2 material with κ≈25, which allows achieving higher capacitance with thinner effective oxide thickness without the need to excessively thin the interfacial SiO2 layer, thereby preserving carrier mobility.
3Stress or pressure
If conventional HfO2-based high-κ dielectric gate stacks are used, then higher capacitance is achieved, but interfacial SiO2 scavenging is required which causes leakage and mobility issues
Solution Approach 1:
Instead of completely removing the interfacial SiO2 layer (excessive action), the patent applies a partial action by selectively scavenging only the excess SiO2 that forms above the desired thickness, leaving the critical 8-10 nm layer intact. This partial removal achieves the desired EOT reduction while preserving the protective SiO2 interface.
Solution Approach 2:
The high-κ HfO2 layer acts as an intermediary that enables capacitance enhancement without requiring complete removal of the interfacial SiO2 layer. The HfO2 layer with its high dielectric constant provides the necessary capacitance boost, allowing the SiO2 layer to remain as a protective interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The HfO2—ZrO2 superlattice gate stacks provide a path for advanced gate oxide structures with significantly lower leakage current and no mobility degradation, enabling energy-efficient electronic devices by achieving a lower effective oxide thickness and enhanced capacitance.
Implementation Method 1
HfO2—ZrO2 superlattice heterostructures with mixed ferroelectric-antiferroelectric order
Implementation Method 2
HfO2—ZrO2 superlattice heterostructures with mixed ferroelectric-antiferroelectric order
Implementation Method 3
stabilized using atomic layer deposition
Data Source
AI summary
Disclosed are HfO2—ZrO2 superlattice heterostructures such as a gate stack (24), stabilized with mixed ferroelectric-antiferroelectric order. directly integrated onto silicon (Si) transistors and scaled down to ˜20 Å. the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is ˜6.5 Å effective SiO2 thickness, which is even smaller than the interfacial SiO2 thickness (8.0-8.5 Å) itself. and the resulting large capacitance cannot be achieved in conventional HfO2-based high-κ dielectric gate stacks without scavenging the interfacial SiO2. which has adverse effects on the electron transport and gate leakage current. Accordingly. the disclosed gate stacks (24), which do not require such scavenging. provide substantially lower leakage current and no mobility degradation and demonstrate that HfO2—ZrO2 multilayers with competing ferroelectric-antiferroelectric order, stabilized in the sub-2 nm thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond the conventional HfO2-based high-κ dielectrics.