Superlattice Gettering Layer for Metal Ion Trapping in Semiconductor Devices
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Solution Overview
Problem
Semiconductor devices face challenges with metal contamination during processing, particularly during aggressive thinning of stacked chip structures, where conventional gettering layers fail to effectively trap and prevent metal diffusion into the device layer, leading to yield loss.
Innovation Solution
A superlattice gettering layer is formed on the front side of a semiconductor substrate, comprising stacked groups of semiconductor monolayers with non-semiconductor monolayers constrained within the crystal lattice, which epitaxially grows an active semiconductor layer and forms metal interconnects, trapping metal ions released during processing and thinning, thereby preventing contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional gettering layers are used during aggressive thinning of stacked chip structures, then manufacturing process can be simplified, but metal contamination occurs and device yield decreases
Solution Approach 1:
The invention uses a composite superlattice structure consisting of alternating semiconductor and non-semiconductor monolayers (e.g., Si and O, or Si and C). This composite structure combines the benefits of semiconductor compatibility with enhanced metal ion trapping capability of non-semiconductor layers, effectively preventing metal contamination during aggressive thinning processes while maintaining ease of manufacture through epitaxial growth.
Solution Approach 2:
The invention changes the physical and chemical parameters of the gettering layer by using ultra-thin monolayer structures with specific atomic compositions. The superlattice structure creates unique electronic and physical properties that enhance metal ion trapping while allowing aggressive thinning. The alternating layers create potential wells that trap metal ions, preventing them from migrating into device regions during processing.
2Productivity
If aggressive thinning is applied to stacked chip structures, then device integration density increases, but metal ions are released and contaminate the device layer
Solution Approach 1:
The superlattice gettering layer acts as an intermediary barrier between the bulk substrate and the device layer. The non-semiconductor monolayers within the superlattice structure serve as trapping sites for metal ions released during aggressive thinning, preventing these harmful ions from reaching and contaminating the device layer. This intermediary structure enables high integration density while blocking metal contamination pathways.
Solution Approach 2:
The superlattice structure creates a nanoscale porous or layered architecture with alternating semiconductor and non-semiconductor monolayers. This structure provides numerous interfaces and trapping sites that capture metal ions released during aggressive thinning, preventing their migration into device regions while allowing the process to proceed with high integration density.
3Reliability
If superlattice gettering layer with non-semiconductor monolayers is formed, then metal ion trapping efficiency increases, but manufacturing complexity increases
Solution Approach 1:
The invention replaces complex mechanical or chemical gettering methods with a epitaxially grown superlattice structure. The alternating semiconductor and non-semiconductor monolayers create inherent potential wells that passively trap metal ions through quantum mechanical effects and chemical affinity, eliminating the need for complex active gettering mechanisms while achieving superior trapping efficiency.
Solution Approach 2:
The superlattice structure segments the gettering function into multiple ultra-thin monolayer interfaces rather than using a single thick layer. Each interface between semiconductor and non-semiconductor monolayers acts as an independent trapping site, collectively providing enhanced metal ion capture capability. This segmented approach achieves high trapping efficiency with minimal total thickness, reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The superlattice gettering layer effectively reduces metal contamination, enhancing device mobility and yield by maintaining metal ions within the substrate, even during aggressive thinning, and providing a stable interface for high-K dielectrics, reducing scattering effects and improving device performance.
Implementation Method 1
the superlattice gettering layer effectively reduces metal contamination, enhancing device mobility and yield by maintaining metal ions within the substrate
Implementation Method 2
reducing scattering effects and improving device performance
Data Source
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AI summary
A semiconductor device may include a semiconductor substrate (102) having a front side and a back side opposite the front side, and a superlattice gettering layer (104) on the front side of a semiconductor substrate. The superlattice gettering layer may include stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The device may further include an active semiconductor layer (106) on the superlattice gettering layer (104) opposite the semiconductor substrate (102), at least one semiconductor circuit (108) in the active semiconductor layer, at least one metal interconnect layer (113, 114) on the active layer, and at least one metal through-via (112) extending from the at least one metal interconnect layer to the back side of the semiconductor substrate. The superlattice gettering layer may further include gettered metal ions.