Superlattice Interface Layer for Low-Resistance Semiconductor Contacts

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Solution Overview

Problem

Advanced CMOS devices face challenges in achieving shallow junctions with low resistance, as doped source and drain regions in ultra-thin Si suffer from excessive sheet resistance and high contact resistance, which is not adequately addressed by existing contact technologies like Schottky S/D MOSFETs.

Innovation Solution

A semiconductor device with a superlattice interface layer between the semiconductor and metal layers, comprising stacked groups of semiconductor and non-semiconductor monolayers, which reduces resistance and enhances charge carrier mobility by modifying energy band structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If doped source and drain regions are used in ultra-thin Si, then junction depth is reduced, but sheet resistance and contact resistance increase excessively

Engineering Contradiction:
Improvejunction depthVSAvoidcontact resistance
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent introduces an ultra-thin insulator layer (i.e., SiNx) as an intermediary between the metal and the semiconductor. This intermediary layer purportedly lowers the Schottky barrier and reduces the S/D resistance by a factor of 5000 in Mg contacts to moderately-doped n-type Si, thereby resolving the contradiction between shallow junctions and low contact resistance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent creates a composite structure consisting of metal layer, ultra-thin insulator layer (SiNx), and doped semiconductor regions. This composite material approach combines the advantages of each material: the metal provides low resistance, the ultra-thin insulator reduces the Schottky barrier, and the doped semiconductor provides the necessary electrical properties, thereby achieving both shallow junctions and low contact resistance.

Inventive Principle:
Principle #40Composite materials

2Reliability

If Schottky S/D MOSFETs are used, then doped S/D regions are replaced with metal, but excessive Schottky barriers remain between S/D and channel

Engineering Contradiction:
Improvecontact resistanceVSAvoidSchottky barrier
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an ultra-thin insulator layer (i.e., SiNx) as an intermediary between the metal and the semiconductor. This intermediary layer purportedly lowers the Schottky barrier and reduces the S/D resistance by a factor of 5000 in Mg contacts to moderately-doped n-type Si, thereby resolving the contradiction between shallow junctions and low contact resistance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The superlattice interface layer significantly reduces resistance and improves charge carrier mobility, allowing for higher performance in semiconductor devices by providing a lower conductivity effective mass and acting as an insulator to prevent dopant diffusion, thereby enhancing device mobility and reducing unwanted scattering effects.

Implementation Method 1

reduces resistance and enhances charge carrier mobility by modifying energy band structures

Methodology Applied
Scientific EffectEnergy band structure modification:

Implementation Method 2

acting as an insulator to prevent dopant diffusion

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS7928425B2Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
Publication Date: 2011.04.19 ATOMERA INC
  • US7928425B2 patent drawing
  • US7928425B2 patent drawing
  • US7928425B2 patent drawing

AI summary

A semiconductor device which may include a semiconductor layer, and a superlattice interface layer therebetween. The superlattice interface layer may include a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.