Superlattice Isolation Structure for Thermal-Safe GAA Fin Fabrication

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Solution Overview

Problem

The challenge in semiconductor manufacturing is to form superlattice structures on a substrate without thermal damage during high-temperature processing, which can degrade the structural integrity of the semiconductor layer and impact device performance and reliability.

Innovation Solution

A method is developed to form superlattice structures on a sacrificial substrate with embedded isolation structures, allowing for high-temperature processing before forming the substrate, which involves forming a stack with the superlattice structure, flipping it, and removing the sacrificial substrate to prevent thermal damage, and includes specific steps like etching and deposition processes to create fin structures and gate-all-around configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If superlattice structures are formed on a substrate during high-temperature processing, then device performance and reliability improve, but thermal damage occurs to the semiconductor layer causing structural degradation

Engineering Contradiction:

Improvedevice reliabilityVSAvoidsemiconductor layer structural integrity

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent forms the superlattice structure on a sacrificial substrate before the semiconductor layer is fully formed or before final device assembly. This preliminary formation allows the superlattice to undergo high-temperature processing that improves its electrical properties and device reliability, while the sacrificial substrate protects the semiconductor layer from thermal damage. The sacrificial substrate is later removed to complete the device structure.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If high-temperature processing is applied to form superlattice structures, then device performance improves, but thermal agglomeration occurs degrading the semiconductor layer

Engineering Contradiction:

Improvedevice performanceVSAvoidthermal agglomeration

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a sacrificial substrate as an intermediary between the superlattice structure and the semiconductor layer. This intermediary allows high-temperature processing to be applied to the superlattice structure for improved device performance, while the sacrificial substrate absorbs or shields against the harmful thermal effects that would cause agglomeration in the semiconductor layer. The sacrificial substrate is subsequently removed after serving its protective function.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If conventional manufacturing processes are used, then manufacturing time and cost are reduced, but thermal damage to the semiconductor layer occurs

Engineering Contradiction:

Improvemanufacturing efficiencyVSAvoidsemiconductor layer integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent segments the manufacturing process into distinct stages: forming the superlattice structure on a sacrificial substrate, processing the semiconductor layer separately, and then combining them. This segmentation allows each component to be optimized independently - the superlattice can undergo necessary high-temperature processing for reliability, while the semiconductor layer is protected during these steps. The additional steps involving the sacrificial substrate are integrated into the existing manufacturing flow to minimize impact on productivity.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of superlattice structures without degrading the semiconductor layer, improving device performance and reliability by preventing thermal agglomeration and current leakage, while optimizing manufacturing time and cost.

Implementation Method 1

forming superlattice structures on a sacrificial substrate with embedded isolation structures, allowing for high-temperature processing before forming the substrate

Methodology Applied

Scientific EffectThermal insulation: Thermal Insulation

Implementation Method 2

includes specific steps like etching and deposition processes to create fin structures and gate-all-around configurations

Methodology Applied

Scientific EffectEtching:

Implementation Method 3

includes specific steps like etching and deposition processes to create fin structures and gate-all-around configurations

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS20230386925A1Semiconductor Device With Isolation Structures

Publication Date: 2023.11.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method of fabricating a semiconductor device with superlattice structures on a substrate with an embedded isolation structure is disclosed. The method includes forming an etch stop layer on a substrate, forming a superlattice structure on the etch stop layer, depositing an isolation layer on the superlattice structure, depositing a semiconductor layer on the isolation layer, forming a bi-layer isolation structure on the semiconductor layer, removing the substrate and the etch stop layer, etching the superlattice structure, the isolation layer, the semiconductor layer, and the bi-layer isolation structure to form a fin structure, and forming a gate-all-around structure on the fin structure.