Superlattice Depletion Layer for High-Mobility Non-Volatile Memory
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Solution Overview
Problem
Existing semiconductor devices do not fully leverage advanced materials and processing techniques to achieve optimal performance in terms of charge carrier mobility and device efficiency.
Innovation Solution
The development of a semiconductor memory device that incorporates a superlattice structure within the depletion layer of memory cells, featuring stacked groups of layers with non-semiconductor monolayers and trap source atoms, which enhances charge carrier mobility and facilitates charge trapping for improved memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor structures are used, then manufacturing is simpler, but charge carrier mobility is insufficient
Solution Approach 1:
The semiconductor layer is segmented into multiple thin monolayers alternating with non-semiconductor monolayers, forming a superlattice structure. This segmentation creates multiple interfaces that reduce scattering effects and enhance charge carrier mobility while maintaining manufacturability through epitaxial growth processes.
Solution Approach 2:
The patent employs composite material structures by combining semiconductor monolayers with non-semiconductor monolayers to form a superlattice. This composite approach leverages the beneficial properties of both materials to achieve enhanced charge carrier mobility through reduced scattering and improved interface quality.
2Speed
If advanced superlattice structures are implemented, then charge carrier mobility improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes critical parameters including monolayer thickness, composition ratios, and growth conditions to achieve the desired superlattice structure. By carefully controlling these parameters during epitaxial growth, the patent achieves enhanced charge carrier mobility while maintaining manufacturability through established semiconductor processing techniques.
3Productivity
If non-volatile memory with trap sources is created, then memory efficiency improves, but device complexity increases
Solution Approach 1:
The superlattice structure serves multiple functions simultaneously: it enhances charge carrier mobility through reduced scattering, provides trap sources for non-volatile memory operation, and maintains compatibility with standard CMOS fabrication processes. This multi-functionality improves memory efficiency without proportionally increasing device complexity.
Solution Approach 2:
The non-semiconductor monolayers act as intermediaries between semiconductor layers, providing trap sites for charge storage while maintaining the crystalline structure integrity. This intermediary role enables non-volatile memory functionality within the superlattice without requiring separate memory structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves charge carrier mobility by reducing scattering effects and enhancing the quality of semiconductor-insulator interfaces, leading to more efficient memory device performance.
Implementation Method 1
This approach significantly improves charge carrier mobility by reducing scattering effects
Implementation Method 2
trap source atoms within the plurality of stacked groups of layers... facilitates charge trapping for improved memory operations
Data Source
AI summary
A method for making a memory device may include forming an array of memory cells on a semiconductor substrate. Each memory cell may include a first well on the semiconductor substrate having a first conductivity type, a second well adjacent the first well and having a second conductivity type and defining a depletion layer with the first well, and a superlattice within the depletion layer. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions, and trap source atoms within the stacked groups of layers. Each memory call may also include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.