Superlattice Memory Cell With Integrated Diode
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Solution Overview
Problem
In crosspoint memory devices, the integration of a pn junction diode to prevent erroneous selection of unselected cells increases film thickness and degrades element characteristics due to property variations, making it challenging to achieve a compact and reliable memory structure.
Innovation Solution
A crosspoint memory device is designed with a superlattice memory cell comprising alternately stacked GeTe and Sb2Te3 layers, where a thin n-type Si layer forms a pn junction with the Sb2Te3 layer, reducing diode thickness and property variation by using a series circuit with the superlattice memory cell, and allowing for a simplified manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pn junction diode is connected to the memory cell to prevent erroneous selection, then the reliability is improved, but the film thickness increases
Solution Approach 1:
The patent merges the diode structure with the memory cell structure by forming the pn junction directly within the memory cell stack. The n-type semiconductor layer is integrated between the bottom electrode and the phase-change layer, eliminating the need for a separate diode structure and reducing overall film thickness while maintaining selectivity functionality.
Solution Approach 2:
The patent transitions from a planar diode connection to a vertical integration approach within the memory cell stack. By stacking the n-type semiconductor layer, p-type semiconductor layer, and phase-change layer vertically, the design achieves compact integration in the thickness direction while preserving the diode's selective function.
2Reliability
If a pn junction diode is connected to the memory cell, then the reliability is improved, but the element characteristics are degraded due to property variation
Solution Approach 1:
The diode and memory cell are merged into a single integrated structure where the n-type and p-type semiconductor layers form the pn junction within the memory cell stack. This integration ensures that the diode and memory cell share the same fabrication process and material properties, reducing variability and improving manufacturing precision.
Solution Approach 2:
The patent optimizes the thickness and doping concentration of the n-type and p-type semiconductor layers to achieve consistent electrical characteristics across all memory cells. By carefully controlling these parameters during fabrication, the design minimizes property variations while maintaining reliable selectivity.
3Volume of stationary object
If the diode thickness is reduced for compact integration, then the volume is reduced, but the manufacturing precision becomes more challenging
Solution Approach 1:
The patent specifies optimized thickness ranges for the n-type semiconductor layer (5 nm to 50 nm) and p-type semiconductor layer (5 nm to 30 nm) to achieve the right balance between compactness and manufacturability. These parameter optimizations ensure that even at reduced thickness, the layers can be reliably fabricated with acceptable precision using standard thin-film deposition techniques.
Solution Approach 2:
The patent employs thin-film deposition techniques to create uniformly thin semiconductor layers with precise thickness control. By using advanced thin-film fabrication methods, the design achieves compact layer thicknesses while maintaining manufacturing precision through process control and material uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a highly integrated three-dimensional memory with reduced diode thickness and variation, improving the overall performance and scalability of the memory device while maintaining low power consumption through Ge atom position switching.
Implementation Method 1
In the superlattice memory cell, by the movement of Ge atoms in the layered crystal, the resistance can be varied
Implementation Method 2
a pn junction diode for preventing erroneous selection of unselected cells must be connected to either of the electrodes of the memory cell
Data Source
AI summary
According to one embodiment, a memory includes a resistance change layer includes a first chalcogenide layer, and a second chalcogenide layer having a composition different from that of the first chalcogenide layer which are stacked alternately, and the resistance change layer having a superlattice structure, and a semiconductor layer of a first conductivity type provided on a one of main surfaces of the resistance change layer.