Super-lattice Phase Change Memory Device with Integrated Electrodes
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Solution Overview
Problem
Current variable resistance memory devices face challenges in reducing manufacturing costs while maintaining effective data storage capabilities, particularly in transitioning between high- and low-resistance states for phase change memory elements.
Innovation Solution
The proposed memory device incorporates a super-lattice phase change memory element with a specific crystalline structure and electrode configuration, utilizing chalcogen compounds and a unique layout to minimize interference between data bits and reduce manufacturing complexity by eliminating the need for additional metallic layers, thereby optimizing the transition between resistance states and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional variable resistance memory devices are used, then data storage capability is achieved, but manufacturing cost is high
Solution Approach 1:
The patent merges the variable resistance element structure with the electrode configuration, where the first and second electrodes are integrated into the memory cell structure. This consolidation eliminates the need for separate additional metallic layers that would otherwise be required, thereby reducing manufacturing steps and costs while maintaining data storage functionality through the phase change mechanism of the chalcogen compound layer.
Solution Approach 2:
The electrodes in this patent serve multiple functions: they act as both the structural framework for the memory cell and the variable resistance element simultaneously. The first electrode, chalcogen compound layer, and second electrode combination provides both the mechanical structure and the phase change functionality, eliminating the need for dedicated separate layers for each function, thus reducing manufacturing complexity and cost.
2Reliability
If additional metallic layers are added to improve memory performance, then data storage reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent combines the electrode structure with the variable resistance element structure, where the first and second electrodes are formed as part of the memory cell fabrication process without requiring additional metallic layer deposition steps. This merging of functions reduces the number of manufacturing layers and steps while ensuring reliable data storage through the phase change mechanism.
Solution Approach 2:
The patent extracts the essential functionality of additional metallic layers by using the existing electrode structure to serve dual purposes. Instead of adding separate metallic layers for electrode and variable resistance functions, the design takes out the redundant layers by making the electrodes themselves form the variable resistance element through the chalcogen compound layer integration.
3Quantity of substance
If bit density is increased, then storage capacity is improved, but interference between bits increases
Solution Approach 1:
The patent applies local quality by confining the phase change material (chalcogen compound layer) to specific localized regions between the first and second electrodes. This localized configuration ensures that the resistance change occurs only in the intended memory cell area, preventing interference with adjacent bits while maintaining high storage capacity through efficient use of space.
Solution Approach 2:
The memory structure is segmented into discrete memory cells, each with its own first electrode, chalcogen compound layer, and second electrode. This segmentation isolates the resistance change phenomenon to individual cells, preventing cross-talk and interference between adjacent bits, while the overall array provides high storage capacity through the multiplicity of segmented cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for efficient data storage with minimal interference between bits, enabling high-speed reading and writing operations while reducing manufacturing complexity and costs, resulting in a compact and cost-effective memory device.
Implementation Method 1
a phase change of a super-lattice, a change of a crystalline state
Implementation Method 2
a change of a crystalline state
Implementation Method 3
filament forming performed through ionic conduction
Data Source
AI summary
According to one embodiment, a memory device includes a first diffusion layer region on, a second diffusion layer region, a third diffusion layer region, a first gate electrode and a second gate electrode. The memory device also includes a first via contact group, a second via contact group and a variable resistance element. At least one of the plurality of first via contacts is electrically connected to the first diffusion layer region with one end and at least one of the plurality of second via contacts is electrically connected to the third diffusion layer region with one end. The variable resistance element being electrically a first interconnect layer.