Superlattice Phase Change Memory Device Layout
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Solution Overview
Problem
Current resistance change type memory devices face challenges in reducing manufacturing costs while maintaining reliability and uniformity, particularly in the formation and etching processes, which affect the size and consistency of memory cells.
Innovation Solution
The proposed memory device configuration includes a substrate with a first active area, three gate electrodes, and upper and lower interconnects, featuring a superlattice-type phase change memory device that uses a specific crystal structure and chalcogen compounds to transition between low and high resistance states, facilitating data storage and reducing manufacturing complexity by optimizing the layout and interconnect distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional resistance change type memory devices are used, then data storage functionality is achieved, but manufacturing cost is high and manufacturing complexity is increased
Solution Approach 1:
The memory device is segmented into distinct functional regions: a first active area for forming resistance change devices and a second active area for forming transistors. This segmentation allows independent optimization of each region's manufacturing process, simplifying overall fabrication by separating the complex resistance change device formation from transistor formation.
Solution Approach 2:
The resistance change devices are extracted as separate entities formed in a dedicated first active area, rather than being integrated with transistor formation in the same region. This extraction enables specialized processing for resistance change devices using chalcogenide compounds, reducing manufacturing complexity while maintaining functionality.
2Manufacturing precision
If resistance change devices are formed with precise control, then uniformity and reliability are improved, but manufacturing precision requirements increase complexity
Solution Approach 1:
The first active area is specifically designed with local quality characteristics suitable for resistance change device formation, including specific material deposition (chalcogenide compounds) and structural features. This localized optimization ensures uniformity and reliability of resistance change devices without requiring the entire manufacturing process to meet high precision standards.
Solution Approach 2:
The resistance change devices are formed in advance in the first active area before transistor formation in the second active area. This preliminary action allows precise control and optimization of resistance change device properties (such as phase change material deposition) to be completed before subsequent transistor fabrication, ensuring uniformity without increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a compact, reliable, and cost-effective memory device with improved manufacturing efficiency, reduced material costs, and enhanced data storage capabilities by minimizing the number of processing steps and ensuring uniformity in resistance change device formation.
Implementation Method 1
a superlattice-type phase change memory device that uses a specific crystal structure and chalcogen compounds to transition between low and high resistance states
Data Source
AI summary
According to one embodiment, a memory device includes a first active area, formed on the substrate, which extends in a third direction. The memory device also includes three gate electrodes, provided on the first active area, which extend in a second direction intersecting the third direction. The memory device also includes at least two or more upper-layer interconnects and at least two or more lower-layer interconnects, provided on the first active area, which extend in a first direction intersecting the second direction and the third direction. The memory device also includes first transistors of three, each of them is provided at the intersection point between the first active area and the three gate electrodes. The memory device also includes the first transistors of three are one device isolation transistor and two cell transistors.