Superlattice Source/Drain Structure for Dopant Diffusion Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in enhancing charge carrier mobility and reducing dopant diffusion, which affects device performance and efficiency.
Innovation Solution
The implementation of a semiconductor superlattice structure with alternating semiconductor and non-semiconductor monolayers, forming a barrier to dopant diffusion and improving the quality of semiconductor-insulator interfaces, thereby enhancing charge carrier mobility and providing piezoelectric, pyroelectric, and ferroelectric properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor structures are used, then manufacturing is simpler, but charge carrier mobility is lower due to scattering effects and dopant diffusion
Solution Approach 1:
The source/drain region is segmented into multiple alternating monolayers of semiconductor material (e.g., Si, Ge) and non-semiconductor material (e.g., SiO2, HfO2), creating a superlattice structure. This segmentation reduces dopant diffusion by confining dopants within specific monolayers and reduces scattering effects through improved interface quality, thereby enhancing charge carrier mobility despite the increased structural complexity.
Solution Approach 2:
The superlattice structure employs composite materials by combining semiconductor monolayers (providing charge transport pathways) with non-semiconductor monolayers (providing barrier properties). This composite approach creates a material system that simultaneously achieves low dopant diffusion and high charge carrier mobility, resolving the contradiction between reliability improvement and structural complexity.
2Manufacturing precision
If dopant diffusion is not restricted, then manufacturing process is simpler, but device performance degrades due to dopant spreading
Solution Approach 1:
The superlattice structure is formed preliminarily before dopant introduction, creating a pre-configured barrier architecture that confines dopants to specific regions. This preliminary action of building the alternating monolayer structure enables precise dopant concentration control during subsequent doping processes, as dopants are naturally confined within the semiconductor monolayers by the non-semiconductor barriers.
Solution Approach 2:
The non-semiconductor monolayers act as intermediary barrier layers between dopant source and the semiconductor channel region. These intermediary layers prevent unwanted dopant diffusion while allowing controlled dopant introduction into the semiconductor monolayers, thereby improving manufacturing precision without excessive processing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The superlattice structure enhances charge carrier mobility by reducing scattering effects and dopant diffusion, improving device performance and efficiency, while also providing beneficial electrical properties for various semiconductor devices.
Implementation Method 1
U.S. Pat. No. 5,357,119 to Wang et al. discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice
Implementation Method 2
forming a first superlattice laterally adjacent the stack on a first side thereof and extending from the substrate to an upper surface of the stack to define a first source/drain region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions
Data Source
AI summary
A method for making a semiconductor device may include forming a stack of alternating gate and nanostructure layers above a substrate, and forming a first superlattice laterally adjacent the stack on a first side thereof and extending from the substrate to an upper surface of the stack to define a first source/drain region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The non-semiconductor monolayers of the first superlattice may be arranged along growth rings extending outwardly from respective adjacent nanostructure layer portions.