CMOS Image Sensor Superlattice Transistor Mobility
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Solution Overview
Problem
Current semiconductor devices, such as CMOS image sensors, face limitations in achieving enhanced performance due to constraints in charge carrier mobility and scattering effects, despite advancements in strained materials and superlattice structures.
Innovation Solution
The use of a superlattice structure with stacked semiconductor monolayers and non-semiconductor monolayers constrained within the crystal lattice, which reduces the effective mass of charge carriers and acts as an energy band-modifying layer, enhancing mobility and providing insulation against dopant diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If strained material layers (silicon, silicon-germanium) are used to enhance carrier mobility, then device speed and power performance are improved, but manufacturing complexity and material quality control become more difficult
Solution Approach 1:
The channel layer is segmented into multiple thin monolayers (first semiconductor monolayer, non-semiconductor monolayer, second semiconductor monolayer) stacked in sequence. This segmentation allows each layer to be precisely controlled and deposited separately, achieving the desired strain and mobility enhancement while maintaining manufacturing feasibility through standard epitaxial growth processes.
Solution Approach 2:
The patent employs a composite structure combining semiconductor materials (first and second semiconductor monolayers) with non-semiconductor materials (non-semiconductor monolayer) to form a superlattice. This composite approach enables simultaneous achievement of carrier mobility enhancement through strain and effective mass reduction, while the non-semiconductor layer provides diffusion barriers and structural stability.
2Speed
If superlattice structures with multiple monolayers are implemented, then charge carrier mobility is enhanced through reduced effective mass, but device structure becomes more complex
Solution Approach 1:
The channel is divided into a superlattice structure with repeated units of semiconductor and non-semiconductor monolayers. Each monolayer is only a few nanometers thick, allowing precise control of strain and effective mass. This segmentation creates multiple interfaces that enhance carrier mobility while the periodic structure maintains manufacturability through standard epitaxial techniques.
Solution Approach 2:
The patent changes the physical parameters of the channel by introducing a superlattice structure with specific monolayer thicknesses and compositions. The non-semiconductor monolayer thickness and semiconductor monolayer thickness are precisely controlled to achieve desired strain levels and effective mass reduction, thereby enhancing carrier mobility without excessive structural complexity.
3Reliability
If non-semiconductor monolayers are inserted in the superlattice, then dopant diffusion is blocked and mobility is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The non-semiconductor monolayer acts as an intermediary barrier between dopant regions. It physically blocks dopant diffusion while maintaining the structural integrity of the superlattice. This intermediary layer is deposited using atomic layer deposition or molecular beam epitaxy, which provide precise thickness control at the monolayer level, achieving both diffusion blocking and manufacturing feasibility.
Solution Approach 2:
The patent replaces traditional mechanical dopant diffusion barriers with a quantum-mechanical approach using thin-film superlattice structures. The non-semiconductor monolayer provides diffusion blocking through its material properties and interface effects rather than through thick physical barriers, enabling precise control with minimal thickness and reduced manufacturing complexity.
4Speed
If thinner monolayers are used in the superlattice, then scattering effects are reduced and mobility increases, but manufacturing precision and defect control become more challenging
Solution Approach 1:
The superlattice structure is designed to be self-healing and defect-tolerant. The periodic arrangement of semiconductor and non-semiconductor monolayers creates a regular pattern that can accommodate and distribute defects uniformly, preventing localized defect accumulation. The thin monolayer design reduces the absolute number of defects while the superlattice periodicity provides a framework for defect management, maintaining high mobility without excessive manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved charge carrier mobility, reduced scattering effects, and enhanced performance in CMOS image sensors by lowering the conductivity effective mass and providing a direct energy bandgap, leading to reduced noise and increased device efficiency.
Implementation Method 1
a superlattice on the first semiconductor layer including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and the superlattice may further include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions
Implementation Method 2
The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices
Implementation Method 3
Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility
Data Source
AI summary
A method for making a CMOS image sensor may include forming an active pixel sensor array including pixels, each including a photodiode and read circuitry coupled to the photodiode and including transistors defining a 4T cell arrangement. At least one of the transistors may include a first semiconductor layer and a superlattice on the first semiconductor layer including a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The transistor(s) may also include a second semiconductor layer on the superlattice, spaced apart source and drain regions in the second semiconductor layer defining a channel therebetween, and a gate comprising a gate insulating layer on the second semiconductor layer and a gate electrode on the gate insulating layer.