SUPERMADD Instruction for Vector Data Processing Throughput
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Solution Overview
Problem
Modern microprocessors face inefficiencies in processing vector data, particularly in graphics and compute-intensive workloads, due to the need for multiple instructions and extensive arithmetic computations, despite the presence of vector units and execution units.
Innovation Solution
A user-level vector instruction, known as the SUPERMADD operation, is introduced to perform multiply-multiply-add operations efficiently on vector data, reducing the number of required operations and increasing throughput by leveraging commonality in these operations, specifically optimized for graphics processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple separate instructions are used to perform multiply-add operations on vector data, then the operations can be completed with existing hardware, but the processing time increases and throughput decreases
Solution Approach 1:
The patent combines multiple separate multiply-add operations into a single fused instruction (VFNMADD231PS) that performs two multiplications and two additions in one execution cycle. This merging of operations eliminates the need for multiple separate instructions and reduces the total number of execution cycles required, directly addressing the throughput and timing issues with vector data processing.
Solution Approach 2:
The invention creates a universal execution unit capable of performing multiple vector operations (multiplications and additions) within a single instruction cycle. This multi-functional approach allows the same hardware resources to handle complex vector computations that previously required sequential execution of multiple specialized instructions, thereby improving productivity without proportionally increasing hardware complexity.
2Ease of manufacture
If traditional vector units are used for graphics processing, then basic vector operations can be performed, but the number of required instructions and arithmetic computations remains excessive
Solution Approach 1:
The patent merges multiple arithmetic operations (two multiplications and two additions) into a single fused instruction that executes atomically. This reduces the total instruction count and simplifies the software implementation while the underlying hardware is optimized to execute this fused operation efficiently, thereby reducing both instruction complexity and operational complexity simultaneously.
Solution Approach 2:
The invention changes the operational parameters of the execution unit by introducing a new fused multiply-add instruction format with specific operand configurations. This parameter change enables the execution unit to perform complex vector operations in fewer cycles by altering how the operations are structured and executed, reducing the overall computational burden without increasing device complexity.
Data Source
AI summary
In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple multipliers and adders, and to execute a user-level multiply-multiply-accumulate instruction to populate a destination storage with a plurality of elements each corresponding to an absolute value for a pixel of a pixel block. Other embodiments are described and claimed.