Superposition Signaling Codes for Chip-to-Chip Pin-Efficiency
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Solution Overview
Problem
Current chip-to-chip communication systems face challenges in achieving high pin-efficiency, low power consumption, and resilience against common-mode noise and SSO noise while maintaining a small physical footprint, as existing differential signaling methods are limited by pin-efficiency of 0.5 and require increased power to combat noise and attenuation.
Innovation Solution
The implementation of superposition signaling codes, which involve encoding information using a set of signals that include quiescent and nonquiescent vector components, allowing for pin-efficiencies greater than 1.0 and minimizing SSO noise introduction, with a driver architecture that matches the signaling code to enhance noise resilience and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional differential signaling methods are used, then noise resilience is achieved, but pin-efficiency is limited to 0.5 and power consumption increases
Solution Approach 1:
The patent changes the fundamental parameters of the signaling scheme by using superposition codes where multiple codewords are combined through addition modulo q. This allows achieving pin-efficiency greater than 1.0 while maintaining noise resilience through the inherent properties of the superposition coding scheme and the use of quiescent and nonquiescent vector components.
2Use of energy by moving object
If power consumption is reduced, then energy efficiency improves, but noise resilience deteriorates
Solution Approach 1:
The patent employs superposition signaling codes with specific parameters (alphabet size q, code length n, number of layers l) that are optimized to achieve both low power consumption and noise resilience. The use of quiescent vector components allows the system to maintain signal integrity with reduced power expenditure.
3Productivity
If pin-efficiency is increased beyond 1.0, then communication bandwidth improves, but SSO noise and common-mode noise increase
Solution Approach 1:
The patent applies local quality by using quiescent vector components that have zero or near-zero signal levels on certain wires during specific time periods. This localized zero-signal approach minimizes SSO noise and common-mode noise generation on those specific wires while maintaining high overall pin-efficiency through nonquiescent components on other wires.
Data Source
AI summary
A communication system uses a bus to transmit information, by receiving signals and mapping them to a second set of signals representing codewords of a superposition signaling code, and transmitting the second set of signals. The superposition signaling code can comprise more than one layer. The pin-efficiency can be larger than 1. The system may encode bits into a codeword of a superposition signaling code that is defined by two basis vectors of predetermined size and then have two encoders for permutation modulation codes defined by the basis vectors. The bits of information are divided into a first part representing a predetermined number of bits and a second part representing a predetermined number of bits, with the parts provided to the respective encoding circuits and their outputs combined by a superposition.