Superscalar CPU Online Testing via Architectural Estimation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for testing superscalar CPUs are inadequate as they require detailed information about internal design and implementation, which is often unavailable, making it difficult to apply existing testing methods to modern superscalar CPUs, especially in safety-critical systems where malfunctions can be hazardous.
Innovation Solution
A method that estimates architectural items of a superscalar CPU based on its general architecture, allowing for pseudo random testing without specific hardware information, ensuring comprehensive testing by choosing test instructions and data that cover all estimated architectural items with high statistical certainty, thus enabling safe operation in safety-critical systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pseudo random testing is applied to superscalar CPUs, then testing coverage is improved, but the method becomes inapplicable without detailed internal design information
Solution Approach 1:
The patent introduces an intermediary layer of architectural specifications and interface definitions that mediate between the test system and the CPU internal structure. By testing through standardized architectural interfaces rather than direct internal access, the method achieves comprehensive testing without requiring proprietary internal design information, thus resolving the contradiction between testing coverage and information requirements
Solution Approach 2:
The patent creates a virtual model or copy of the CPU's architectural behavior based on publicly available specifications. This architectural model serves as a substitute for the actual internal hardware, allowing pseudo-random testing to be applied to the model without needing access to the physical internal structure, thereby maintaining testing effectiveness while eliminating the need for detailed internal design information
2Adaptability or versatility
If conventional testing methods are used, then detailed internal design information can be utilized, but the methods cannot be applied to modern superscalar CPUs
Solution Approach 1:
The patent develops a universal testing methodology that works across different superscalar CPU architectures through standardized architectural interfaces. By designing tests that operate at the architectural level rather than the implementation level, the method becomes universally applicable to modern superscalar CPUs regardless of their specific internal designs, thus achieving versatility without relying on proprietary internal information
3Reliability
If startup/online testing is performed, then CPU malfunction can be detected, but the testing cannot be performed without architectural scope estimation
Solution Approach 1:
The patent performs preliminary architectural scope estimation before executing the actual testing sequence. By analyzing the CPU's architectural specifications in advance and determining the scope of architectural items to be tested, the method prepares a comprehensive test plan that ensures all relevant components are covered during startup or online testing, thus enabling reliable malfunction detection while managing the complexity through advance planning
Data Source
Figure 1
Figure 2
AI summary
The invention relates to a method for testing a superscalar CPU (=central processing unit) of a computer system, wherein the testing is done during startup (11) of the computer system and/or online during operation of the computer system, characterized in that the testing comprises a pseudo random testing procedure (1-8), wherein pseudo random test instructions and pseudo random test data are fed to the superscalar CPU (4a, 4b), and wherein an output data signature of the superscalar CPU is compared to a reference data signature (7). The invention provides a testing method for a superscalar CPU of a computer system that can be applied with basically every superscalar CPU, in particular even if detailed information about internal design and implementation of CPU hardware is not available.